Featured below are links to some recent articles about MIPS Technologies. Read on to see what reporters, editors and industry analysts are saying.

Single-chip coherent multiprocessing is next step

Director of Product Marketing for MIPS’ Processor Business Group, Mark Throndson, describes how SMP platforms and software can provide a flexible, high-performance computing platform that delivers significant speedup relative to single processors, often with little or no application code modification. Read the article here.

MIPS Moves on Multi-Core: MIPS32 1004K

In the website’s lead story the week of April 2^nd, Editor Kevin Morris takes and in-depth look at the MIPS32 1004K Coherent Processing System. According to Morris, “The challenge of keeping all your cores busy in a symmetric multi-processing (SMP) system is actually made much easier when the multi-processor is combined with multi-threading.” Read more on the Embedded Technology Journal website here.

MIPS rolls first multiprocessing core

EE Times Editor Rick Merritt gives an overview of MIPS’ new MIPS32® 1004K™ Coherent Processing System, wrapping up his article with a quote from respected industry analyst Linley Gwennap, “There are a lot of embedded multicore processors out there but not that many licensable multiprocessing cores... This helps people design multicore chips quickly without needing to develop the underlying logic.” Read more of this article on the EE Times website here.

Multiprocessor system sports up to four coherent, multi-threaded cores

Technical Editor Robert Cravotta discusses the technical features of the 1004K CPS, saying, “The nine-stage pipeline architecture of the MIPS32 1004K coherent processing system will support a worst-case 800-MHz base core operating frequency, in a TSMC 65-nm GP process.” Read more on the EDN website here.

MIPS combines multi-threading with coherent multicore IP

In one of the most in-depth articles to-date on the 1004K CPS, Editor Richard Goering discusses the product’s technical and market impact. According to the article, “The 1004K CPS is a ‘significant release’ for MIPS, said Christian Heidarson, principal analyst for the semiconductor group at Gartner. He said it’s the first licensable multi-threaded, multi-processor IP core he’s aware of.” Read more here.

MIPS launches first multi-processing core

In this Electronics Weekly cover story, Editor Steve Bush discusses the 1004K CPS, saying, “Applications are foreseen initially in second-generation Blu-ray players which include facilities like picture-in-picture, fast printers, and Internet gateways with advanced security features.” Read more on the Electronics Weekly website here.

Interfacing High Performance 32-bit Cores To MCU-based Memory Architectures

MIPS Technologies’ Senior Applications Engineer Bob Martin describes how simple instruction pre-fetch buffers and i-cache systems placed into 32-bit MCU designs can have a profound effect on improving MCU performance. He discusses techniques system architects can employ when upgrading their MCU architecture from 16-bit to a 32-bit core CPU. Read the article here.

MIPS Adds Hot Spot Analyzer for MIPS32 Cores

In this article, Electronic Design editors describe the new Hot Spot Analyzer (HSA), an Eclipse plug-in that provides non-intrusive profiling of software running on MIPS32 cores. The analyzer is built on the unique Zero Overhead Program Counter Sampling feature that is included in MIPS® cores. Read more on the Electronic Design website here.