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 What are the biggest challenges today for SoC developers when integrating connectivity solutions?
 When I was studying and building digital systems back in school, the biggest challenge was to find adequate discrete components so that at the board level we could connect them together— the assumption being that each discrete chip component was robust and acting according to specification. The main concern was always the interface, and how flexible it was. Typically I had an FPGA in the system so that we could adapt the different interfaces in the system.
The biggest challenge today remains essentially the same, but instead of discrete chip components, we have IP. With the huge increase in complexity required to implement modern, multi-function SoCs, the integration effort is a major bottleneck. Connectivity IP typically includes a digital controller (MAC) as well as a physical layer (PHY) comprised of mixed-signal circuitry. As the industry moves to lower process nodes (e.g. 45nm) for SoCs, designers are challenged to meet their performance targets for the analog portions of their design in technology nodes that are optimized for the digital portion. To avoid costly re-spins and meet time-to-market goals in this environment, it is important that designers select IP that is mature and proven, backed by development and support teams with deep integration knowledge.
How can MIPS Technologies help?
As an IP vendor, we’re laser-focused on reducing integration effort and risk for our customers. MIPS Technologies has developed—and is continuously expanding—our embedded peripheral solutions, with a combination of hard IP, soft IP and firmware that isolates complexity and mitigates the risk of integrating advanced connectivity solutions.
I was visiting with a customer the other day, and was told that the fact that we can provide pre-validated solutions integrating the PHY and controller is a great relief for their engineers. By having access to a complete solution, they no longer have to learn the specifics of each internal interface between the PHY and controller. We completely insulate the customer from those details, and therefore they can concentrate on overall system integration.
What are MIPS’ Embedded Peripheral Solutions?
MIPS’ Embedded Peripherals are a combination of digital IP (controllers), analog IP (physical layers or PHYs), and software—complete solutions aimed at simplifying our customers’ effort and time when integrating connectivity functions onto the SoC.
We are well aware of the difficulties in bringing complex analog functions together within the SoC, and that’s why our objective is to combine those analog functions with digital functions that are interfaced to the system using a standard interface, such as AMBA or OCP.
This strategy is fully implemented in the USB area, where we offer a very extensive and complete portfolio, including new versions supporting Link Power Management (LPM) and High-Speed Inter-Chip (HSIC) USB, and we are applying the same concept in other areas, such as HDMI and DigRF.
What is your vision for Embedded Peripherals?
We have a very ambitious vision. First, we want to expand our portfolio with other standardized IP interfaces, and in the long-term, we plan to expand this vision to include other functions such as audio converters and sensors.
We intend to facilitate the integration of analog functions by presenting a layer of digital functions so that it becomes, in logical terms, as simple as integrating another peripheral into the system bus. See the picture below. I think this concept is very powerful.
MIPS Technologies’ Embedded Peripherals Vision
Why choose MIPS Technologies’ connectivity IP solutions?
There is a long list of very compelling reasons to choose MIPS’ solutions. I will describe a few of the most important.
One of the biggest reasons to choose MIPS Technologies’ solutions is that our silicon-proven and certified connectivity IP solutions reduce risk for our customers. In addition, our customer commitment includes a dedicated customer support program to assist in all stages of design integration, with the overall objective of successful production.
Another reason is that we have a broad portfolio of complete and proven connectivity solutions that are available for major open foundries, as well as many captive integrated device manufacturers (IDMs) in process technologies from 0.18um down to 40nm. We are continually expanding these offerings in alignment with our customers’ roadmaps.
We also offer perfectly matched PHY-controller combinations, with controllers available as RTL source code. The IP comes with guaranteed interoperability, reducing risk in integration of IP from different providers. Optimized for lower power consumption, our IP cores are ideal for portable/mobile applications. Our controllers have the most effective set of features, designed for easy system-level integration. Compact area leads to reduced silicon usage.
Another reason is our broad, innovative and proven portfolio, including our USB IP offering that has proven success among our customers. In fact, we have more than 80 USB customers worldwide and more than 30 USB 2.0 certified products in mass production. More than 200 million chips have been produced to-date with Chipidea USB 2.0 solutions.
One more reason is that we preempt market needs. MIPS Technologies was first in the market to certify USB IP in TSMC 65LP, first in the market to launch USB IP in 45nm and 40nm, and also first in the market to launch a number of new products, namely a USB OTG controller, USB PHYs using 1.8 and 2.5V transistors, High-Speed Inter-Chip (HSIC) USB PHY, and USB controllers with Link Power Management (LPM) support. There are currently 25 certified USB IP cores that are published on the USB-IF website.
With all of these reasons, customers can feel confident in choosing MIPS Technologies as a trusted connectivity IP partner.
What is MIPS’ Connectivity Roadmap?
The next big challenges for the industry in terms of connectivity IP are in multimedia and chip-to-chip communications, and we are already looking ahead to address these challenges. A customer that I visited recently told me,“ when I tell you what I will need for my next generation product, I’m sure that you are already working on it!”
And he is right. We do align our product roadmap with our customer expectations for new connectivity IP, and we are also already working far in advance of current market trends to maintain our competitive advantage.
In the short term, we are planning to cover additional connectivity standards including MIPI DSI, MIPI CSI, DigRF 4G,
DisplayPort Tx
and Rx, and USB 3.0. In the medium- and long-term, we’ll have much more.
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