About the Author: Colin Baldwin is Open-Silicon’s Director of Marketing. He has 15 years of ASIC design and sales experience with Texas Instruments, Arrow Electronics, and Open-Silicon. Mr. Baldwin received both BEE and MSEE degrees from Georgia Tech.

Open-Silicon recently completed physical design of a custom ASIC using the MIPS32® 24Kc™ processor core, a synthesizable 32-bit RISC CPU with an eight stage pipeline. The 24Kc core has numerous configuration options for speed, area and power that put it in high demand for many consumer electronics and wireless applications. This particular project required fast time to market plus maximum performance; the 24Kc was an excellent fit.

To balance the time to market and performance tradeoffs, a two-pass flow was used. The first pass utilized a MIPS® layout methodology, which employs industry-standard EDA tools and which carefully tunes area, power consumption and performance while still providing primary emphasis on maximum speed. The second pass took the results of the first pass and applied Open-Silicon’s proprietary CoreMAX™ technology, which specializes in optimizing the performance of embedded processors.

With CoreMAX, Open-Silicon’s processor optimization team uses over two million lines of Open-Silicon developed C++ software and several patented techniques to move beyond the limitations of traditional library-based ASIC design. CoreMAX techniques include design Boolean analysis, static timing, cell placement, route estimation and simultaneous optimization at the logical, physical and transistor levels. Based on the needs of each critical path in the design, CoreMAX may change cells, move cells, or even create new cells on-the-fly, performing a library-compatible layout for each new cell and characterizing them for use throughout the EDA environment. These new cells offer unique drive strengths and functionality that enable maximum device performance.

Both implementations were done using 32Kbyte data and instruction caches in a TSMC90G 90nm process with standard Vt and Virage libraries. The baseline implementation was performed using the recommended floorplan from MIPS Technologies and the supplied design flow for Magma BlastFusion™. A maximum clock rate of 518 MHz was measured using 100ps jitter, 8% OCV, worst-case corner, worst-case parasitics, and SI in PrimeTime-SI®.

The CoreMAX implementation was then run by comparison to see how the additional library cells created on-the-fly impacted the timing. A maximum clock rate of 550 MHz was obtained using the same signoff conditions. This represents an overall performance increase of 6.2%, which is in the range of the 6-10% performance improvement historically seen across over 50 previous CoreMAX processor optimizations.

Spending additional effort to maximize processor performance is not needed for every application, yet for some ICs, obtaining maximum processor performance offers a compelling market benefit. Others have found that CoreMAX allows them to achieve the design’s required performance using a density-optimized library, or using a standard Vt transistor instead of dual Vt (standard, low) devices, saving device cost and power. Open-Silicon is continuing to invest in its unique transistor-level cell-optimization technology to enable customers needing maximum performance, or minimum power, to bring their designs to market.