Debug Technologies
Benefits of MIPS® PDtrace™
MIPS® PDtrace™ is an extension to the EJTAG debug architecture. It was developed as a response to the increasing sophistication of debug requirements for highly integrated MIPS-Based™ designs. PDtrace is very beneficial for hardware debug/bring-up and considered by many as indispensable for software development. A quick summary of the benefits include:
- Supports address triggers that can be qualified by a bit-wise mask.
- Execution instruction trace is useful to look back to see where the code executed at the instruction, source line, or even function level. It shows the exact path the code took through if-then-else conditionals, case statements, and while loops.
- The ability to turn trace on and off allows the trace buffer to be better utilized for capturing the execution of the function or functions of interest.
- Program code can be traced in one or more of the specific privilege modes allowed by a core implementation.
- PDtrace supports use of the address space identifier (ASID) as a trigger/filter to identify program code that will be traced.
- Set data triggers on the value of a variable residing at a specific address. The data values can be qualified by byte-wise masking values.
- Detect hard to track code errors such as null pointers or writes to non-existent memory
- Access of the variables can be qualified by masking access to specified byte-lanes, or by allowing triggering to occur on any cycle access or only on Load or Store access.
- Trace can be qualified on just store addresses, store with data values, or include load addresses and optional data values. This storage control provides optimal utilization of the trace buffer.
- Choose between an on-chip trace buffer, off-chip, or both.
- on-chip for small-to-moderate trace depths; useful for debugging the cause of problems leading up to exceptions or breakpoints
- off-chip trace accommodates deep trace probes which can provide post-acquisition analysis. Suited for FPGA-based prototypes which generally have sufficient pins.
- both - inexpensive EJTAG probe for access to on-chip trace buffer; off-chip trace tap for extensive software analysis. An ASIC with both can target high-volume designs (no trace connector) as well as development and evaluation boards
- Post process the real-time trace buffer for performance optimization.
- Deep traces can be post-processed to provide performance analysis by binning executed address occurrences to reveal hot-spots or, with timestamps, the duration of each function.
- The same trace can be analyzed for code coverage to help develop regression tests to cause all the code to execution (and even keep track of branches taken and not taken).
- Cache misses can be tagged with PDtrace and post-processed to illuminate cache thrashing.
- Collect cycle accurate information which is useful when trying to determine the exact operation of the core, cache and memory subsystem. Higher counts of idle clock cycles indicate cache misses - instruction or data loads.
PDtrace Debug Features for the MIPS32® 34K™
- Halt and single step one VPE while the other VPE continues to run
- Halt and single step one TC at a time.
- View the context of each TC
- View TC registers and stack pointer, determine the call stack and parameters and the source context of where the TC halted.
- Set breakpoints that include a specific TC id and execution address
- Supports debug for cases where multiple TCs share code
- Trace capture includes the TC id for each trace cycle and the trace window shows the order of TC execution through the pipeline.
- Color coded to easily distinguish which TC executed on each clock cycle
- Filtered trace to show a single TC
- Display illuminates when a memory stall occurred and another TC executed while the memory value was being fetched.
- Shows the results of the hardware policy manager that controls the amount of cycles that each TC receives
