Bringing MIPS to the Masses

MIPS' innovations for microcontrollers (MCUs) and other cost-sensitive, low-footprint embedded applications continue with the introduction of two new processor cores in the MIPS32® 4K® core family. The new MIPS32 M14K™ and M14Kc™ cores are the first MIPS32-compatible cores to incorporate the new microMIPS™ code compression Instruction Set Architecture (ISA). Both cores implement the MIPS32 Release 2 architecture, and are designed from the same 5-stage pipeline 4K microarchitecture—achieving a high performance efficiency of 1.5DMIPS/MHz.

M14K Core: High Performance for 32-bit Microcontrollers
A superset of the M4K core, the M14K core retains all of its features including a high-performance SRAM controller, 32 general purpose registers, shadow register sets, fast multiply/divide unit and fixed mapping MMU. MIPS also maintained optional building blocks to provide coprocessor and user defined instruction (UDI) extensions.

The M14K core builds on the capabilities of the M4K core with additional features to reduce interrupt latency and context switching time, and accelerate access to flash memory-resident code, enhancing the real-time performance and code execution of typical MCU applications. The M14K core also has build-time options to include additional high-end trace/profiling capabilities and a standard AHB-Lite bus controller that provides for improved system development and reduced time to market.

The M14K core achieves 90% higher performance, 40% smaller size and 25% less power than the ARM Cortex-M3 on a like-for-like comparison (90nm).

Figure 1 is a block diagram of the M14K core.

Figure 1: MIPS32 M14K block diagram. Optional features are shown as green blocks, retained features from the M4K core are shown in gray callouts, and new/enhanced features are shown as purple callouts.

M14Kc Core for High-Performance Embedded Digital Home Applications
The M14Kc core is an extension of the MIPS32 4KEc® core, maintaining the same high performance, programmable cache controller, translation lookaside buffer (TLB) MMU, and exceptional Linux and Java performance. It is designed to satisfy the requirements of high-performance, cost-sensitive consumer and communications-centric electronics, including DTVs, set-top boxes, DVD players, wired/wireless network access points, and mobile and personal entertainment devices.

The M14Kc core includes the reduced interrupt latency, advanced debug and additional atomic-bit instructions features that are also present in the M14K core. The M14Kc core also includes the AHB-Lite bus controller as a standard feature, additional MMU security attributes and support for optional parity detection for the I- and D-caches.

Both the M14K and M14Kc core provide a high degree of build-time and configurability options.

In a like-for-like comparison with ARM9 at 90nm, the M14Kc core achieves 15% higher performance, 25% smaller size and 28% less power.

Figure 2 is a block diagram of the M14Kc core.

Figure 2: MIPS32 M14Kc block diagram. Optional features are shown as green blocks, retained features from the 4KEc core are shown in gray callouts, and new/enhanced features are shown as purple callouts.

microMIPS Advanced Code Compression ISA
At the heart of the M14K and M14Kc cores is the new microMIPS ISA that offers uncompromised MIPS32 performance with a high level of code density. Executing microMIPS will reduce code memory size by up to 35% while maintaining 98% of MIPS32 performance—resulting in significant silicon cost savings.

Figure 3 shows the relative microMIPS vs MIPS32 performance and code size results from a set of Dhrystone and CSiBe benchmarks.

Figure 3: microMIPS vs MIPS32 benchmark performance and code size

microMIPS is a complete ISA providing both 16- and 32-bit instructions in a single, unified instruction set, supporting both MIPS32 and MIPS64® Release 2 Architectures. microMIPS re-encodes existing MIPS32 instructions, includes 15 new 32-bit instructions, and converts 39 existing frequently-used MIPS32 instructions into new 16-bit instructions. microMIPS also includes all MIPS ASE instructions and supports the CorExtend™ UDI extensions.

The M14K and M14Kc cores have a dual-decoder design that incorporates both the MIPS32 and microMIPS instruction decoders, supporting microMIPS and legacy MIPS32 code. The dual decoder design is implemented in the existing 4K microarchitecture and maintains the efficiency of the 5-stage pipeline structure. The smaller code footprint of microMIPS leads to better cache utilization and lower fetch bandwidth, helping to improve performance and reduce power consumption.

Development Tools

M14K and M14Kc SoC development is supported by a comprehensive set of hardware and software development tools from MIPS Technologies, with additional support available from an extensive third party partner ecosystem.

microMIPS code development support is provided by the Eclipse-based CodeSourcery Sourcery G++ GNU software toolchain including compiler, assembler, debugger and libraries. The Sourcery G++ toolchain is available for bare-iron/RTOS and Linux targets in Lite, Personal and Professional editions.

Hardware and software co-development support is enabled by the MIPS Navigator™ Integrated Component Suite (ICS) that integrates Sourcery G++, support for MIPS System Navigator™ probes and other debug and profiling plug-ins. The System Navigator probe provides extensive debug and profiling capabilities for M14K- and M14Kc-based designs, incorporating a high speed 50 MHz EJTAG interface.

A new FPGA-based evaluation/development board called SEAD-3 has been developed specifically to enable rapid prototyping and testing of M14K and M14Kc designs.

Future third party support for microMIPS has been announced from industry leading software development providers including RTOS and Linux support from Express Logic Thread-X®, Micrium uC/OS-II, Mentor Nucleus and Linux, MontaVista Linux 6, Timesys Linux, and co-simulation models from Carbon Design Systems and Imperas.

Production release of M14K and M14Kc cores is scheduled for late Q1 2010, and evaluation systems will be available starting in December 2009. Further information, including datasheets, product briefs and white papers are available at www.mips.com/microcontrollers.