SmartMIPS® ASE
Today's smart cards must support multiple applications and deliver uncompromising levels of security. The SmartMIPS extensions to the MIPS32® architecture, jointly defined with Gemplus SA - the world's number one provider of smart cards - provide a complete solution, delivering unparalleled security and cryptography performance.The SmartMIPS architecture marries cryptography enhancements, Secure Memory Spaces, code compression and virtual machine performance enhancements to enable an inexpensive, low-power and complete smart card processor solution.
- The SmartMIPS architecture's cryptography enhancements speed public- and secret-key data security algorithms, eliminating the need for dedicated coprocessors, and reducing die size and total system cost
- Software cryptography allows easy field upgrades of cryptography algorithms. Therefore, a potential breach in the security algorithm doesn't require a recall of the actual cards
- Accelerated software cryptography enables choice of algorithm (such as RSA, DES, AES, and elliptic curve cryptography (ECC) ) on a per-application basis
- Secure Memory Spaces protect sensitive consumer data by application, preventing unauthorized data access by rogue applications
- Code-compression minimizes memory use, preserving scarce memory resources
- Designed to support and accelerate key operating systems such as Sun Microsystems' Java Card™ technology and Microsoft's Windows for Smart Cards
MIPS Technologies' Software Cryptography Strategy
Today's security technology using dedicated hardware coprocessors is inadequate for next-generation multi-function smart cards. The need for longer keys and newer, more secure algorithms such as AES and elliptic curve cryptography require more flexible cryptography solutions than fixed-function hardware blocks allow. The high performance software-based cryptography enhancements in the SmartMIPS architecture allow a wide choice of algorithms and permit reuse rather than replacement of deployed smart cards when algorithms change. The SmartMIPS architecture was designed to support a wide variety of algorithms, including RSA, DES, AES, and elliptic curve cryptography. The SmartMIPS architecture provides the flexibility demanded by next-generation multi-function smart cards.
Support for Interpreted Language Acceleration
Multi-function smart cards require platforms that support interpretive languages. This strategy provides a portable and secure framework for multi-application smart cards. However, there are competing interpretive languages that fulfill this requirement. MIPS Technologies has chosen to provide maximum flexibility to licensees by extending the SmartMIPS architecture in ways that accelerate interpretation in general, rather than any one interpretive language.
Secure Memory Spaces
Smart cards are subject to all manners of attacks that endeavor to compromise their integrity. A smart card architecture must increase overall system security and not provide a point of vulnerability. The architecture must support secure programming and secure operating systems. The SmartMIPS architecture is specifically designed to provide all the memory management mechanisms necessary to support secure programming and verifiably secure operating systems. User code is separated from system code; applications can be encapsulated in their own memory areas and execute-, read-, and write-only page-protection attributes are individually programmable.
- Defines a set of features for secure computing environments such as those found in smart cards; these features include:
- Cryptographic algorithms for encryption key generation
- Secure instruction execution
- MMU features for small memory systems
- Enables lower-cost systems by eliminating the need for dedicated coprocessors
- Software-based cryptography allows in-the-field upgrades of algorithms without hardware recalls
- Accelerated software cryptography allows algorithm choice such as RSA, DES, AES, and elliptic curve cryptography (ECC) on a per-application basis
- Extended accumulator for polynomial math operations
- Polynomial multiply and multiply-accumulate operations
- Partial permutation instruction
- Register rotate instructions
- Base_Register+Scaled-Index_Register addressing for virtual machine/interpreted-language environments
- Read-Inhibit and Execute-Inhibit TLB attribute bits to support execute-only or read-only pages
- Support for 1KB TLB pages for memory-constrained systems
MIPS32® Architecture for Programmers Volume IV-d: The SmartMIPS® Application-Specific Extension to the MIPS32® Architecture (.pdf)
v3.00 (731 KB)
SmartMIPS™ ASE (.pdf)
See MIPS Run, Second Edition
Author: Sweetman, Dominic
Publisher: Morgan Kaufmann; 2 edition (October 31, 2006)
ISBN-10: 0120884216
ISBN-13: 978-0120884216
MIPS Assembly Language Programming
Author: Britton, Robert
Publisher: Prentice Hall; illustrated edition edition (June 7, 2003)
ISBN-10: 0131420445
ISBN-13: 978-0131420441
The Mips Programmer's Handbook
Author: Bunce, Philip; Farquhar, Erin
Publisher: Morgan Kaufmann; 1st edition (January 15, 1994)
ISBN-10: 1558602976
ISBN-13: 978-1558602977
Real-Time Embedded Multithreading Using ThreadX and MIPS
Author: Lamie, Edward
Publisher: Newnes; Pap/Cdr edition (December 26, 2008)
ISBN-10: 1856176312
ISBN-13: 978-1856176316
Computer Architecture, Fourth Edition: A Quantitative Approach
Authors: Hennessy, John; Patterson, David
Publisher: Morgan Kaufmann; 4 edition (September 27, 2006)
ISBN-10: 0123704901
ISBN-13: 978-0123704900
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