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microMIPS™

microMIPS32 and microMIPS64

microMIPS32 and microMIPS64 are high performance code compression technologies that combine optimized 16- and 32-bit instructions in single, unified Instruction Set Architectures (ISAs). microMIPS32 supports the MIPS32® architecture and microMIPS64 supports the MIPS64® architectures. Both microMIPS ISAs provide uncompromised performance and a high level of code density by incorporating a combination of variable length re-encoding MIPS instruction set and additional code-size optimized 16- and 32-bit instructions.

As a complete ISA, microMIPS can operate standalone or in co-existence with the legacy-compatible MIPS32 instruction decoder, allowing programs to intermix 16- and 32-bit code without having to switch modes. The smaller code footprint of microMIPS leads to better cache utilization and lower fetch bandwidth, helping to improve performance and reduce power consumption.

microMIPS32 – 32x32b registers; 32 bits Virtual Address, up to 36 bits Physical Address (same as MIPS32)

microMIPS64 – 32x64b registers; 64 bits Virtual Address, up to 59 bits Physical Address , adds 64- bit variables (same as MIPS64)

Both microMIPS ISAs support the CorExtend™/UDI interface and include all elements of the MIPS base architecture including virtualization, SIMD (Single Instruction Multiple Data) and multi-threading (MT) as well as DSP extensions and EVA (Enhanced Virtual Addressing). microMIPS software and system development are supported by a comprehensive set of hardware and software tools provided by MIPS Technologies and an ecosystem of third party partners. microMIPS was initially implemented in the M14K/Kc™ family and is also leveraged in the new microAptiv™ processor core family.

A code compression ISA that maintains 98% of MIPS32 performance while reducing code size by 35%, translating to significant silicon cost savings
Developed in both MIPS32 and MIPS64 architecture-compatible formats—the unified ISA has 16- and 32-bit opcodes in the MIPS32 version and additional 48-bit opcodes in the MIPS64 version
Optimized opcode and operand field definitions based on statistical analysis of a wide range of application software, middleware, RTOS and Linux kernel
MIPS assembly source code level and ABI compatible
Maintains MIPS' proven compiler efficiency in code generation

Supports all existing MIPS32 and MIPS64 instructions (Branch Likely instructions are emulated by the MIPS assembler. These instructions are in MIPS32/64 but removed in microMIPS32/64)
A well supported software ecosystem that has been built up over that time to support a broad range of market segmentsWidely used in multiple segments - home entertainment, wired and wireless networking, mobile devices, storage and more
A clean architecture allows for a wide range of implementations, from cost-constrained microcontrollers to supercomputers
Fixed-sized 32-bit instructions allow easy instruction decode
32 x 32-bit General Purpose Register file; optional shadow register sets
Robust load/store RISC instruction set with 3-operand instructions in most formats (3 registers, 2 registers + immediate), branch/jump options, and delayed jump instructions

Simple addressing modes allow for higher frequencies and simpler implementations
Flexible software management for stack operations
Delayed branches aid in efficient coding

No integer condition codes allows for easier superscalar implementations
Optional Modules of the Base Architecture

MIPS SIMD architecture (MSA) module provides more computational capability for a wide range of applications
Scalable Virtualization (VZ) module provides secure hardware virtualization
Multi-threading provides high throughput processing
DSP technologies for media processing

Support for 8-bit, 16-bit, 32-bit and 64-bit variables
Floating Point Specifications

Optional single and double-precision floating point supportIEEE-754-2008 Floating-Point specification support
Provision for 32 x double-precision 64-bit Floating-Point Registers

Compatibility

Fully supports Big-Endian and Little-Endian systems
Fully MIPS I™ and MIPS II™ ISA compatible
Upward compatible with MIPS64 architecture

Specific Instructions

Enhanced with conditional move and data-prefetch instructions
Standardized DSP operations: multiply (MUL), multiply and add (MADD), and count leading 0/1s (CLZ/O)
Rotate instructions
Integer multiply, divide support
Bit-field insert/extract instructions

Interoperability with microMIPS™Optional Memory Management Unit (MMU) with:

TLB or BAT address translation mechanisms
Programmable page size
Flexible software management of Page Table walk
Increased security with execute inhibit and read inhibit pages
Enhanced page-table handling
Enhanced Virtual Addressing (EVA) with support for multi-gigabyte physical address spaces
Virtual Memory segments with programmable attributes