MIPS32® Architecture

The MIPS32® Architecture sets a new performance standard for 32-bit embedded processors. It is the foundation of MIPS Technologies' roadmap for next generation high-performance MIPS-Based™ processors, SoCs and provides upward compatibility to the MIPS64® 64-bit architecture. The MIPS architecture is the leading embedded architecture because of its robust instruction set, scalability from 32-bits to 64-bits, broad-spectrum of software development tools and widespread support from numerous MIPS Technologies licensees. The MIPS32 architecture is a superset of the previous MIPS I™ and MIPS II™ Instruction Set Architectures (ISA) and incorporates powerful new instructions, specifically for embedded applications, as well as proven memory management and privileged mode control mechanisms previously found only in 64-bit R4000™ and R5000® MIPS® processors. By incorporating powerful new features, standardizing privileged mode instructions, and supporting past ISAs, the MIPS32 architecture provides a solid high-performance foundation for all future 32-bit MIPS-Based development.

The MIPS32 architecture is based on a fixed-length, regularly encoded instruction set and uses a load/store data model. The architecture is streamlined to support optimized execution of high-level languages. Arithmetic and logic operations use a three-operand format, allowing compilers to optimize complex expressions formulation. Availability of 32 general-purpose registers enables compilers to further optimize code generation for performance by keeping frequently accessed data in registers.

The MIPS32 architecture derives the privileged mode exception handling and memory management functions from the popular R4000 and R5000 class 64-bit processors. A set of registers reflects the configuration of the caches, MMU, TLB, and other privileged features implemented in each core. By standardizing privileged mode and memory management and providing the information through the configuration registers, the MIPS32 architecture enables real-time operating systems, other development tools, and application code to be implemented once and reused with various members of both the MIPS32 and the MIPS64 processor families.

Flexibility of its high-performance caches and memory management schemes continues to be a strength of the MIPS architecture. The MIPS32 architecture extends this advantage with well-defined cache control options. The size of the instruction and data caches can range from 256 bytes to 4Mbytes. The data cache can employ either a write-back or write-through policy. A no-cache option can also be specified. The memory management mechanism can employ either a TLB or a Block Address Translation (BAT) policy. With a TLB, the MIPS32 architecture meets Windows CE and Linux memory management requirements.

The increasing computation needs of the embedded market are met by the addition of intensive data processing, data streaming, and predicated operations. Conditional data move and data cache prefetch instructions were introduced, allowing for improved data throughput in communication and multimedia applications. Fixed-point DSP-type instructions further enhance multimedia processing. These new instructions, that include Multiply, Multiply and Add, Multiply and Subtract, and "count leading 0s/1s," provide greater performance in processing data streams such as audio, video, and multimedia without adding additional DSP hardware to the system.Powerful floating-point instructions speed the tasks of processing some DSP algorithms and calculating graphics operations in real-time. Floating-point operations can optionally be emulated in software. Finally, to ease the task of system integration, the MIPS32 standard defines the optional use of EJTAG (Extended JTAG) as a non-intrusive, on-chip, real-time debug system.