SOC-it® L2 Cache Controller
With time-to-market pressures mounting for complex 90nm and 65nm SoC designs, MIPS Technologies, Inc. has developed a platform strategy for its entire range of MIPS® processors. The fully verified SOC-it® Platform and supporting environments will ease the design of high-performance MIPS-Based™ SoCs, lowering costs, accelerating time-to-market and reducing development risk.The first component of the SOC-it Platform is the SOC-it® L2 Cache Controller, an efficient L2 subsystem. Fully synthesizable and highly portable across processes, the SOC-it L2 Cache Controller works seamlessly with all MIPS Technologies OCP-based cores and uses standard cell libraries and memory arrays. The SOC-it L2 Cache Controller reduces system costs, lowers power consumption and boosts performance by up to 100%.
- Inline OCP device
- Unified cache (I and D combined)
- 32-byte cache line sizeo 8-Way set associative
- Pseudo-LRU replacement algorithm
- Selectable I/O clock ratios
- Support for dual-use as SRAM
Features
- 7-stage pipeline to achieve high frequencies with low power
- Programmable cache sizes
- 128, 256, 512 or 1024 KBytes
- Up to 12 outstanding read misses, with hit under miss
- Write-back and write-through support
- Physically indexed, physically tagged
- Cache line locking support
- Optional ECC support for resilience to soft errors
- Single bit error correction and 2 bit error detection support for Tag and Data arrays
- ingle bit detection only for WS array
- OCP master and slave interfaces
- Compliant to OCP version 2.1
- Bypass mode
- Optional system memory support
- Unified level 2 cache holds instruction and data references
- Power control
- Minimum frequency: 0 MHz
- Sleep mode
- Support for extensive use of fine-grained clock gating
- Easy integration
- Fully synthesizable RTL
- Single-port synchronous SRAMs for tag, data and way-select arrays
- Support for optional pipelined SRAMs for data array
- Testability
- Full scan design achieves test coverage in excess of 99% (dependent on library and configuration options)
- Optional memory BIST for internal SRAM arrays, with support for integrated (March C+, IFA-13) or custom BIST controller
Specifications
| Gate Count | 220K gates (area optimized) |
| Technology | TSMC 90G |
| Cache Size | 256 KB |
| Speed Target | 400 MHz |
| Total Area | 5.2mm2 |
| Core | 1.2mm2 |
| Arrays | 4.0mm2 |
