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MIPS32® 4KE® Family

The highly configurable MIPS32® 4KE® core family provides enhanced capabilities from the previous generation MIPS 4K® family of cores, offering features such as code compression, multiple sets of 32-bit registers, larger write-back cache memories and extensive clock gating. The 4KE core family gives system-on-chip(SoC) designers flexibility to optimize their applications by maximizing performance or minimizing power consumption.

  • The 4KE core family includes the following cores:
    • 4KEp® core - basic version with iterative multiply and small fixed mapping translation (FMT) for memory management unit (MMU)
    • 4KEm® core - 4KEp core plus fast Multiply/Divide Unit,
    • 4KEc® core - 4KEm core plus TLB MMU,
    • 4KEPro cores - 4KE cores with CorExtend™ capabilities
  • MIPS16e™ code compression allows designers to reduce the memory requirements
    for their application by as much as 40%.
  • Cores can be configured with up to 64KB instruction and 64KB writeback data
    cache for more flexibility and higher performance.
  • The highly configurable and synthesizable core enables flexibility for designers to
    include only those features necessary for their application.
  • Extensive clock gating reduces power consumption without reducing application
    performance.
  • BIST, scan and Enhanced JTAG (EJTAG) debug with trace (PDtrace™) and fast
    download enable quick and easy debugging.
  • The 4KE cores are synthesizable and can be ported to any foundry process.
  • All major operating systems and compiler tool chains, and hundreds of third-party
    development tools support the MIPS® architecture.



MIPS32® enhanced (Release 2) architecture

  • 5-stage pipeline
  • 1, 2, 4 or 8 sets of 32-bit general purpose registers
  • Supervisor mode operation
  • Vectored interrupts and support for external interrupt controller
  • Atomic interrrupt enable/disable
  • Bit field manipulation instructions
  • Virtual memory support (small page sizes and hooks for extensive page table manipulation)

MIPS32 privileged resource architecture

  • Count/compare registers for real-time interrrupts
  • I and D watch registers for SW breakpoints

MIPS16e™ code compression

  • Special PC-relative instructions for efficient loading of addresses and constants
  • SAVE & RESTORE macro instructions for setting up and tearing down stack frames within
  • 16-bit encodings of 32-bit instructions to improve code density

Programmable cache sizes

  • Individually configurable instruction and data caches, sizes from 0-64KB
  • Direct mapped, 2-, 3- or 4- way set associative
  • Loads block only until critical word is available
  • Non-blocking prefetches
  • Write-back support
  • 16-byte cache line size

Scratchpad RAM support

  • Can optionally replace 1 way of the I- and/or D-cache with a fast scratchpad RAM
  • 20 index address bits allow access of arrays up to 1MB
  • Interface allows back-stalling the core

Memory management unit (MMU)

  • 32 dual-entry JTLB with variable page size
  • Fixed or TLB-based MMU, dependent on family member

Simple bus interface unit (BIU)

  • All I/O fully registered
  • Separate unidirectional 32-bit address and data buses
  • Two 16-byte collapsing write buffers
  • Designed to allow easy conversion to other bus protocols

Integer multiply/divide unit (MDU)

  • Fast or area-efficient, dependent on family member
  • Maximum issue rate of one 32x16 multiply per clock (fast MDU)
  • Maximum issue rate of one 32x32 multiply every other clock (fast MDU)

General purpose coprocessor (COP2) interface

  • 32-bit interface to an external coprocessor

Power Control

  • Minimum frequency: 0 MHz
  • Power-down mode (triggered by WAIT instruction)
  • Support for software-controlled dock divider
  • Support for extensive use of local gated clocks

EJTAG Debug

  • Support for single stepping
  • Virtual instruction and data address breakpoints
  • PC and data tracing add with trace compression (PDtrace™)
  • Cross-CPU breakpoint support

Development tools

  • MIPS SDE – GNU based toolchain optimized to support MIPS cores
  • MIPSsim™ – bus-functional modeling and instruction-set simulator
  • System Navigator™ probe – EJTAG probe
  • NavigatorIDE – Eclipse-based graphical integrated development environment



Process (nm) 130 90
Frequency - (MHz) worst case 100 - 250 250 - 420
Performance (DMIPS)410 690
Coremark numbers700 1180
Power - (mW/MHz) typical
(core + 8k/8k Caches)
0.32 - 0.68
0.15 - 0.26
Area - (mm2, core + 8K/8K/ Caches)
1.2- 1.90.65 - 1.2

Note: Frequency, power consumption and size depend upon configuration options, synthesis, silicon vendor, process and cell libraries. For 130nm, Worst case is slow silicon, 1.08V, 125C; Typical case is typical silicon, 1.2V, 25C. For 90nm, Worst case is slow silicon, 0.9V, 125C, Typical case is typical silicon, 1.0V, 25C. Quoted speeds don't contain SI, OCV, clock jitter and design margin.


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