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MIPS32® 74K®

The MIPS32® 74K® core family is the industry's first fully synthesizable processor IP to surpass 1.5 GHz in TSMC 40nmG process using industry standard libraries and EDA flows. The 74K® core family is based on a superscalar microarchitecture with out-of-order (OoO) instruction dispatch. The implementation features a 15-stage pipeline to achieve high synthesizable frequencies, and supports up to 4 instructions fetched per cycle, plus up to 4 instructions issued per cycle in the 74Kf core, the version in the family with a dual issue high performance floating point unit (FPU).

MIPS is the leading processor architecture used in consumer entertainment and networking products in the home. Anticipating the emergence of Web-connected flat panel TVs, set top boxes (STB), Blu-ray DVD and related consumer devices, MIPS Technologies recently enhanced the 74K microarchitecture, with increased performance of 20-30% on Javascript, Flash®, and Web page rendering applications.

The innovative embedded microarchitecture also incorporates the MIPS® DSP Application Specific Extension (ASE) Rev2. These instructions, coupled with the 74K microarchitecture, dramatically boost signal processing performance up to 60% when compared to RISC implementations with original DSP ASE in previous generation architectures.

There are two versions available in the 74K core family – the 74Kc (integer core only) and the 74Kf (with high performance FPU), with both versions supporting a variety of configuration options, and use with a separately available SOC-it® L2 cache controller. In addition, the 1074K? Coherent Processing System, a multi-core platform leveraging multiple 74K cores to provide new levels of performance for higher end digital home, networking and portable media applications is now available.

  • A 15-stage asymmetric dual-issue pipeline, out-of-order instruction dispatch/completion and fully synthesizable design gives SoC developers full flexibility to port the design across different processes and accelerate time-to-market
  • Two versions of the 74K family are available - 74Kc™ (standard) and 74Kf™ (high-performance Floating Point Unit)
  • Standard OCP bus interface provides backward-compatibility with existing 24K, 24KE and 34K cores
  • A rich ecosystem of third-party software and debug tools coupled with software and tools support from MIPS Technologies
  • Back-end EDA flow support for Cadence, Magma and Synopsys design tools

Architecture

  • Superscalar asymmetric dual-issue pipeline with out-of-order dispatch and completion
  • 128-bit wide access to the instruction cache and 64- or 128-bit wide access to the data cache
  • Up to 4 instructions fetched per cycle, and up to 4 instructions issued per cycle in 74Kf core with dual issue FPU
  • Combined majority branch predictor using three 256-entry BHT; 8-entry return prediction stack
  • CorExtend™ user-defined instruction set extensions
  • Multiply/divide unit to support maximum issue rate of one 32/32 multiply per clock
  • Low power consumption through the use of fine grain, block level, and top level clock gating
  • Support for Revision 2 of the MIPS32 DSP ASE
  • MIPS16e™ code compression
  • EJTAG debug 3.2 interface and PDtrace™ program and data trace

Floating Point Unit (FPU)

  • IEEE 754-compliant FPU, compliant to MIPS® 64-bit FPU architecture (74Kf version only)
  • Supports single- and double-precision data types
  • Separate in-order, dual-issue pipeline decoupled from integer pipeline

Bus Interface Unit

  • OCP version 2.1 interface with 32-bit address and separate 64-bit read and write data interfaces
  • OCP version 2.1 interface runs at core/bus clock ratios of 1, 1.5, 2, 2.5, 3, 3.5, 4, 5, or 10 via a separate synchronous bus clock

Programmable MMU

  • 16/32/48/64 dual-entry, dual-ported TLB shared by Instruction and Data MMU
  • 4-entry ITLB (4KB, 1MB page size)
  • Optional simple Fixed Mapping Translation (FMT) mechanism

Programmable Cache Sizes

  • Configurable I-Cache (0-64KB) and D-Cache (0-64KB) sizes
  • 4-way set-associative caches with write-back and write-through support
  • 32-byte cache line size
  • Data scratchpad RAM support (4KB-1MB)
  • Extensions for front-side L2 cache

Development Tools

  • MIPS® Navigator ICS - IDE, software toolkit, MIPSsim™, EJTAG and PDtrace probes
  • CodeSourcery - SG++ toolchains for MIPS

Process 65nm GP
Coremark/MHz 2.57
LibrariesTSMC 10 track SVt
Frequency1080 MHz (worst case)
Performance2.03 DMIPS/MHz
Power0.52mW/MHz
Core area1.7mm2 (core only, fully placed and routed)
Total die area2.5mm2 (includes core plus caches)

Both implementations optimized for speed (area and power-optimized specifications available upon request)

Achieved using free standard cells from TSMC and memories from Dolphin; quoted speeds are at worst case slow/slow corner, with signal integrity and production margins of 10% OCV and 50 ps clock jitter.

Note: Frequency, power consumption and size depend upon configuration options, synthesis, silicon vendor and process and cell libraries.

Configuration: 74Kc with 32K/32K caches, 32 entry dual TLB, and no scratchpad


MIPS32® 74K® Core - Simplified Overview