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MIPS32® M14K™

The MIPS32® M14K™ core is a high-performance, compact, low-power design with features that are optimized to deliver a superior solution for microcontroller (MCU) and real-time embedded system applications.

 

The M14K core is the one of the first MIPS32-compatible processor cores to also execute the new microMIPS™ code compression Instruction Set Architecture (ISA). microMIPS delivers an uncompromised level of performance with a high degree of code density. It maintains 98% of MIPS32 performance while reducing code size by 35%, translating to significant silicon cost savings.

A superset of the MIPS32 M4K™ core, the M14K core is fully compatible with MIPS32 Release 2 Architecture. It retains virtually all features of the M4K core, including 32 General Purpose Registers (GPRs), support for shadow register sets, SRAM-type interface controller, Memory Management Unit (MMU) and a high performance Multiply/Divide Unit (MDU). The core design is based on the 5-stage pipeline 4K®micro-architecture, providing a performance efficiency in microMIPS mode of 1.57 DMIPS/MHz and 2.72 CoreMark/MHz.

The M14K core implements application-specific features for MCUs that accelerate access to flash memory, enhance the interrupt handling mechanism and add atomic bit instructions. Designers can leverage an optional AMBA®AHB-Lite™ interface, providing a standard interface to a wide range of compatible peripherals. MIPS Technologies also provides a comprehensive set of advanced debug and profiling features to enable fast time to market. The M14K core is supported by an extensive set of integrated software and hardware development tools and a broad ecosystem of third party partners.

A high-performance, low-footprint microMIPS enhanced processor optimized for efficient and cost-sensitive MCU and real-time embedded applications.

  • Fully compatible with MIPS32 Release 2 Architecture and based on the 5-stage pipeline 4Kmicro-architecture that provides performance efficiency of 1.57 DMIPS/MHz-with a high degree of configurability for application-optimal performance, area and power
  • Implements microMIPS, a unified 16- and 32- bit ISA combining new and recoded MIPS32 instructions for 32-bit performance and near 16-bit code size
  • Application-specific features for MCUs: circuitry and new instructions to the interrupt handler reduce latency, extend the number of priority levels and accelerate vector generation; a configurable pre-fetch buffer scheme speeds up access to flash memory-resident code
  • Expands on existing EJTAG-based debug/trace features to include additional capabilities within iFlowtrace™ and to provide advanced program profiling and event analysis capabilities; real-time debug facility with a bi-directional, low CPU overhead, Fast Debug Channel
  • Comprehensive development support: supported by a complete microMIPS and MIPS32-compatible GNU software toolchain, MIPS® Navigator Integrated Component Suite (ICS), MIPS System Navigator™ debug probe and a FPGA-based development platform

Architecture

  • MIPS32 Release 2 compatible 5-stage pipeline delivering 1.5 DMIPS/MHz
  • MIPS32 compatible instruction decoder
  • Fixed Mapping Translation (FMT) Memory Management Unit (MMU)
  • Configurable Multiply/Divide Unit, single cycle 32x16 and 2 cycle 32x32 multiply
  • Thirty two 32-bit GPRs with an additional option for up to 16 shadow GPRs

microMIPS Instruction Set Architecture

  • Enhanced code compression ISA of combined 16- and 32-bit instructions
  • Supports all existing MIPS32 instructions; adds new 16- and 32-bit instructions
  • Supports co-existence with legacy MIPS32 decoder
  • Supported by software toolchain and hardware development/debug systems

MCU Application Specific Extension (ASE)

  • Implements an enhanced interrupt handling scheme, supporting up to 8 interrupt pins in Vectored Interrupt mode and 255 interrupts in External Interrupt Controller mode
  • Includes hardware features that reduce interrupt latency to 10 cycles
  • Implements logic and new instruction (IRET) to automate and accelerate interrupt return handling operations
  • Supports interrupt chaining
  • Includes 2 new atomic-bit instructions

Flash Memory Access Accelerator (optional)

  • Implements a 2-line pre-fetch buffer to 'cache' flash memory contents
  • Configurable for bit width and memory address range

Bus Interface Unit (optional)

  • Implements AMBA AHB-Lite interface
  • Contains single 32-bit address bus and two unidirectional (R/W) data buses
  • Single bus master with single burst mode support

SRAM-Style Interface

  • 32-bit address and data interface with single or multi latency support
  • Configurable separate or unified instruction (I) and data (D) memory interface
  • Supports connection to 8- and 16- bit memory devices, transaction abort, back-stalling, D- to I- redirection and lock/sync mechanism

EJTAG Debug & Trace (Optional)

  • Supports enhanced iFlowtrace with additional event trace modes
  • Simple instruction & data breakpoint support - 2I/1D, 4I/2D, 6I/2D, 8I/4D
  • Complex breakpoints, instruction & data, with conditional filtering supported
  • Support for 2 Performance Counters (PCs) with multiple event type options
  • PC and data address sampling: zero overhead, qualified read/write
  • Fast Debug Channel provides a low overhead, high bandwidth bi-directional data transfer capability between the target and debug host/probe

Power Management

  • Incorporates extensive fine clock gating
  • Supports software controlled clock frequency divider
  • Implements a Power Down mode initiated by a WAIT instruction

TSMC 90G SVt TSMC 65LP LVt
Speed Opt.Area Opt.Speed Opt.Area Opt.
Frequency (MHz)*305100420150
Core Area (mm2)0.250.0760.140.07
Active Power (mW/MHz)0.070.0250.050.026
Sleep Power (uW/MHz)1.121.061.210.94
Cell Library9T SVt7T HVt9T LVt9T HVt
Note: Frequency, power consumption and size depend upon configuration options, synthesis, silicon vendor, process and cell libraries
* Quoted speeds are PTSI and contain OCV, design margin and clock jitter
** Speed Opt: Std core configuration + microMIPS + MCU ASE + AHB-Lite + Flash Accelerator + Fast MDU
** Area Opt: Std core configuration + microMIPS + MCU ASE + slow MDU


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