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MIPS32® M14Kc™

A superset of the popular MIPS32® 4KEc™ core, the M14Kc processor core is a high-performance, compact, low-power design that delivers a superior solution for cost-sensitive embedded applications such as home entertainment, personal entertainment and home networking. The M14Kc core implements the MIPS32 Release 2 Architecture with a design that is based on the highly optimized 4K® micro-architecture. It incorporates an execution unit with a 5-stage pipeline, delivering performance efficiency in microMIPS mode of 1.57 DMIPS/MHz and 2.72 CoreMark/MHz.

 

The M14Kc core is one of the first MIPS cores to incorporate the microMIPS™ code compression Instruction Set Architecture (ISA). microMIPS offers uncompromised 32-bit performance with exceptional code density by using an optimal combination of 16- and 32-bit instructions. Executing the microMIPS ISA achieves 98% of the performance with a 35% reduction in code size relative to MIPS32-only mode.

The M14Kc core retains all of the features and functionality from the 4KEc core, including 32 General Purpose Registers (GPRs), high performance Multiply/Divide Unit (MDU) and optional coprocessor extension interfaces. It also includes the programmable instruction and data cache controller and Translation Lookaside Buffer Memory Management Unit (TLB MMU) from the 4KEc core.

The M14Kc core incorporates the new MCU ASE, which provides enhancements to interrupt handling logic, reduces interrupt latency and adds atomic-bit instructions. The M14Kc core also has a comprehensive set of advanced debug and profiling features and is supported by integrated software and hardware development tools and a broad ecosystem of third party technologies.

Combining the highly efficient 4KEc base architecture with new and enhanced features makes the M14Kc core a superior solution for Linux, Java and Android applications.

An efficient, cache controller based, real-time processor core utilizing microMIPS to provide a high-performance and low-cost solution for digital home, personal entertainment and networking applications.

  • Efficient base architecture: 100% compatible with MIPS32 Release 2 Architecture, the 5-stage pipeline design delivers performance efficiency of 1.57 DMIPS/MHz
  • Implements microMIPS, a unified 16- and 32- bit ISA including new and recoded MIPS32 instructions for 32-bit performance and near 16-bit code size
  • Application-specific features with reduced interrupt latency, extended interrupt priority and vector control; standard AHB-Lite Bus Interface Unit and optional parity support for cache memories
  • Advanced debug and profiling: expands on existing EJTAG-based debug/trace features with additional iFlowtrace™ capabilities, advanced program profiling, event analysis capabilities and real-time debug
  • Comprehensive development support: supported by a complete microMIPS and MIPS32-compatible GNU software toolchain, MIPS® Navigator Integrated Component Suite (ICS), MIPS System Navigator™ debug probe and a FPGA-based development platform

Architecture

  • MIPS32 Release 2 compatible 5-stage pipeline delivering 1.5 DMIPS/MHz
  • MIPS32 compatible instruction decoder
  • Configurable 16- or 32 dual entry joint TLB MMU or 4 entry I- and D- TLB MMU
  • Configurable Multiply/Divide Unit, single cycle 32x16 and 2 cycle 32x32 multiply
  • Thirty two 32-bit GPRs with an additional option for up to 16 shadow GPRs

microMIPS Instruction Set Architecture

  • Enhanced code compression ISA of combined 16- and 32-bit instructions
  • Supports all existing MIPS32 instructions, adds new 16- and 32-bit instructions
  • Includes support for all MIPS ASEs and CorExtend™ User Defined Instructions
  • Supports co-existence with legacy MIPS32 decoder
  • Supported by software toolchain and hardware development/debug systems

MCU-ASE

  • Implements an enhanced interrupt handling scheme, supporting up to 8 interrupt pins in Vectored Interrupt mode and 255 interrupts in External Interrupt Controller mode
  • Includes hardware features that reduce interrupt latency to 10 cycles
  • Implements logic and new instruction (IRET) to automate and accelerate interrupts return handling operations
  • Supports interrupt chaining
  • Includes 2 new atomic-bit instructions

Programmable cache controller

  • Individually configurable I- and D- caches, sizes range up to 64KB
  • Direct mapped 2-, 3- or 4-way associative
  • Write back and write-through modes

Bus Interface Unit (optional)

  • Implements AMBA® AHB-Lite™ interface
  • Contains single 32-bit address bus and two unidirectional (R/W) data buses
  • Single bus master with single burst mode support

Parity support (optional)

  • Parity detection for I- and D-cache, I- and D- SPRAM

EJTAG debug & trace

  • Supports enhanced iFlowtrace with additional event trace modes
  • Simple instruction & data breakpoint support - 2I/1D, 4I/2D, 6I/2D, 8I/4D
  • Complex breakpoints, instruction & data, with conditional filtering supported
  • Support for 2 Performance Counters with multiple event type options
  • PC and data address sampling: zero overhead, qualified read/write
  • Fast Debug Channel provides a low overhead, high bandwidth bi-directional data transfer capability between the target and debug host/probe

Power management

  • Incorporates extensive fine clock gating
  • Cache memory power saving mode
  • Implements a Sleep mode initiated by a WAIT instruction

TSMC 90G SVtTSMC 65LP LVt
Speed Opt.**Area Opt.**Speed Opt.**Area Opt.**
Frequency (MHz)*316200400150
Core Area (mm)0.50.20.220.14
Active Power (mW/MHz)0.10.050.070.04
Sleep Power (uW/MHz)1.951.31.661.21
Cell Library9T SVt7T HVt9T LVt9T LVt
Note: Frequency, power consumption and size depend upon configuration options, synthesis, silicon vendor, process and cell libraries
* Quoted speeds are PTSI and do not contain OCV, design margin and clock jitter
** Speed Opt: Std core configuration + microMIPS + MCU ASE + AHB + TLB MMU + 8K I&D Cache + Fast MDU
** Area Opt: Std core configuration + microMIPS (area opt) + MCU ASE + AHB + TLB MMU + 8K I&D Cache + slow MDU


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