MIPS Products

MIPS32® 74K™

The MIPS32® 74K™ core family is the industry's first fully synthesizable processors to surpass 1 GHz using industry standard libraries and EDA flows. The 74K™ core family is based on MIPS' latest superscalar microarchitecture with out- of-order instruction dispatch. The innovative embedded microarchitecture also incorporates the MIPS® DSP Application Specific Extension (ASE) Rev2.

These instructions, coupled with a dual -issue 74K microarchitecture, dramatically boost signal processing performance up to 60% when compared to RISC implementations with original DSP ASE in previous generation architectures. The distinguishing feature of the 74K family is that it provides all the essential advantages for high-performance SoC design, while significantly reducing overall die area, cost, and power consumption.

The 74K core family is supported by a robust suite of software development tools, the MIPS DSP Library, and a third party DSP applications network. This enables SoC designers to work in a single design environment and significantly lower system costs by migrating DSP functionality onto a 74K core. The core IP is available in versions with (74Kf core) or without (74Kc core) floating point unit support.


  • Architecture
    The 74K™ core is a revolutionary superscalar embedded microarchitecture with out-of-order instruction dispatch and support for DSP ASE Rev2. It is fully synthesizable, provides highest performance on generic libraries and standard flows. The efficient DSP ASE Rev2 implementation allows the 74K core to act as a DSP-enhanced host core, displacing functionality and dedicated resources from other proprietary processors or DSP cores.

  • Lower cost, design flexibility, faster TTM
    The fully synthesizable configurable design brings tremendous benefits to the SoC designer in performance, cost and time to market.

  • MIPS Ecosystem™
    Based on the industry-standard 74K microarchitecture, the 74K family leverages the existing MIPS32 design ecosystem and targets key applications software from voice to video.

Architecture

  • Superscalar dual issue pipeline with Out-of-Order Instruction dispatch
  • 15-stage pipeline
  • 32-bit address paths and 64-bit data paths to external interface
  • 128-bit data path for instruction cache and 64 or 128-bit data path for data cache
  • 4 instruction fetch per cycle
  • Combined Majority Branch Predictor using three 256 entry Branch History Tables (BHT)
  • 8-entry return prediction stack
  • CorExtend user defined instruction set extensions

DSP ASE Rev2

  • 3 additional pairs of accumulator registers
  • Fractional data types (Q15, Q31)
  • SIMD instructions operate on 216 bit or 48 bit simultaneously

FPU

  • IEEE-754 compliant Floating Point Unit, compliant to MIPS 64-bit FPU standards
  • Supports single- and double-precision data types
  • Optionally runs at 1:1, 3:2 or 2:1 core/FPU clock ratio
  • Separate in-order dual-issue pipeline decoupled from integer pipeline

MDU

  • Maximum issue rate of one 32x32 multiply per clock
  • 7-cycle multiply latency
  • Iterative SRT divide algorithm. Minimum 10 and maximum 50 clock latency (dividend (rs) sign extension-dependent)

Bus interface Unit

  • OCP version 2.1 interface with 32-bit address and 64-bit data
  • OCP version 2.1 interface runs at core/bus clock ratios of 1, 1.5, 2, 2.5, 3, 3.5, 4, 5, or 10 via a separate synchronous bus clock
  • Clock ratio can be changed dynamically
  • Burst size of four, 64-bit beats
  • 4-entry write buffer

Programmable MMU

  • 16/32/48/64 dual-entry, dual-ported TLB shared by Instruction and Data MMU
  • 4-entry ITLB (4KB, 1MB page size)
  • 4K, 16K, 64K, 256K, 1M, 4M, 16M, 64M, 256M byte page size supported in JTLB
  • Optional simple Fixed Mapping Translation (FMT) mechanism

Programmable cache sizes

  • Instruction Cache sizes of 16/32/64 KB
  • Data Cache sizes of 0/16/32/64 KB
  • 4-way set associative
  • 32-byte cache line size
  • Writeback and write-through support in data cache
  • Optional parity support
  • Data Scratchpad RAM support
  • Extensions for front-side L2 cache

Power

  • Minimum frequency: 0 MHz
  • Power-down mode (triggered by WAIT instruction)
  • Support for software-controlled clock divider and support for extensive use of fine-grained clock gating

EJTAG 3.2

  • Support for single-stepping
  • Instruction address and data address/value breakpoints
  • TAP controller is chainable for multi-CPU debug
  • Cross-CPU breakpoint support


Frequency * 1.10 Ghz
Core Area (mm2)1.7
Total Area (mm2)2.5
Performance2.0 DMIPS/MHz
ProcessTSMC 65nm GP
Cache Size (Inst / Data)32K / 32K
Standard CellsTSMC
MemoriesDolphin

*Achieved using free standard cells from TSMC. Quoted speed includes SI, do not include OCV and PLL jitter

Note: Frequency, power consumption and size depend upon configuration options, synthesis, silicon vendor, and process and cell libraries. Configuration: 32K/32K caches, 32 entry dual TLB, no scratch pad



MIPS32® 74K™ Core - Simplified Overview