MIPS32® 24Kc® Hard IP Cores
The MIPS32™ 24Kc™ Hard Core is a technology-specific implementationof the synthesizable 32-bit MIPS32 24Kc core. The implementation is targetedfor the TSMC 0.18µm process. Chip developers or system OEMs who arebuilding complex System-On-Chip ASIC devices can significantly reduce designtime, resources, and time-to-market by using the 24Kc TSMC Hard Core.- 261 MHz in .18µm G TSMC process
- Hard IP cores allow designers to significantly reduce design time, efficiently use resources, and quickly get to market
- Based on MIPS32 architecture for high performance
- 16KB Instruction and 16KB writeback Data cache for more flexibility and higher performance
- Scratchpad interface (up to 1 Mbytes)
- A coprocessor 2 (COP2) interface enables easy coprocessor connection and support
- Extensive clock gating reduces power consumption without reducing application performance
- Enhanced JTAG (EJTAG) debug with trace and fast download enable quick and easy debugging
- All major operating systems and compiler tool chains, and hundreds of third-party development tools, support the MIPS architecture
- Testability features include BIST and full scan
32-bit MIPS32® architecture
- 8-stage pipeline
- 32-bit address
- 64-bit data paths to caches and external interface
- Vectored interrupts and support for external interrupt controller
Scratch pad data ram support
- Independent of data cache configuration
- 64-bit OCP interface for external access, DMA
- Can support arrays up to 1 MB
- Interface allows back-stalling the core pipeline
Memory-management unit (MMU)
- 4 entry instruction TLB
- 8 entry data TLB
- 32 dual-entry joint TLB with variable page sizes
- Optional fixed mapping translation (FMT) for applications not requiring address mapping or protection
Bus Interface Unit (BIU)
- Implements the Open Core Protocol (OCP Release 2.x)
- 64-bit read and write data buses to efficiently transfer data between memory and L1 caches
- 4 entry write buffer
Integer multiply/divide unit (MDU)
- Fully pipelined single-cycle repeat rate for 32X32 MAC instructions
Power control
- Minimum frequency: 0 MHz
- Power-down mode (triggered by WAIT instruction)
EJTAG debug
- Support for single stepping
- Virtual instruction and data address breakpoints
- PC and data tracing
General purpose coprocessor (COP 2) interface
- 64-bit interface to a user defined coprocessor
Development support
- MIPS® SDE GNU based toolchain, MIPSsim™ Instruction Set Simulator, MIPS DSP Library. These tools are licensed for Windows, Linux and Solaris operating systems.
- A complete offering of third-party development tools
| Process | 0.18µm TSMC CL018G |
| Frequency* | 261 MHz1 |
| Core Size | 10.7 sq. mm including caches2 |
*Frequency measured under worst case conditions (SS process corner, Vdd nom - 10%, Tj=125 oC) and with perfect input clock 216K/16K caches
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