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MIPS® Navigator™ Probes



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MIPS Technologies' Navigator™ probes support the latest cores and licensee processors in the MIPS32® family including microAptiv™, interAptiv™, and proAptiv™ cores. It also supports the classic MIPS32 cores from the 4K™ and 4KE™ cores to the 1004K™ coherent processing system. MIPS64® bit cores such as 5K and 20K are also supported.

Navigator probes are designed to support the special features and integrated peripherals of the MIPS family of synthesizable cores. They leverage MIPS EJTAG debug features and also support advanced PDtrace™ features, if present, in the processor implementation. The Navigator probe connects to the target system using a standard 14-pin EJTAG debug connector.

Extensive debugger support including Eclipse-based MIPS® Navigator™ ICS on Windows® and Linux

Software development tools used with the Navigator probes include the Sourcery embedded C/C++ GNU-based toolchain for MIPS and the MIPS® Navigator Integrated Component Suite (ICS). All probe features are available from the Navigator ICS interface, which has an Eclipse-standard interface and C/C++ Development Tool (CDT) components, with special plug-ins for processor debugging using the probe. For more information about the MIPS Navigator ICS, click here.

Key Features

  • Supports microAptiv™, interAptiv™, and proAptiv™ cores
  • Supports MIPS32®, including the M4K™, 4K™, 4KE™, M14K™, M14Kc™, M14KE™, M14KEc™, 24K™, 34K™, 74K™, 1004K™, 1074K™ families
  • Supports MIPS64® bit cores including 5K and 20K
  • Supports multiple source-level debuggers including the Sourcery embedded C/C++ toolchain, MIPS Navigator ICS, and GDB
  • Supports PDtrace in on-chip trace capture mode
  • Real-time PC execution trace, load/store address, and data trace
  • Trace can be gated on/off by on-chip triggers
  • Scalable internal trace depth or external trace port width and speed
  • Supports saving the trace buffer and trace setup information to files and later viewing that trace from a stand-alone dequeuer program
  • Unlimited software breakpoints via SDBBP instruction
  • Single-step by assembly or C source line
  • Read-write all CPU registers
  • Read-write memory whether CPU is stopped or running
  • MIPS standard hardware breakpoints
  • Flash programming support with new algorithms for faster flash programming
  • Multi-core debug with multiple MIPS cores
  • Go, halt processor run control
  • Low-level access to JTAG functions for silicon verification
  • Single line assembler and disassembler
  • Command-line interface with Tcl/tk scripting
  • Binary software interface adheres to MDI specification