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MIPS32® 34K™ Family Architecture & Integration Training Course

Let the experts show you how to take full advantage of processor cores that offer, not only the highest performance and among the lowest power consumption of any 32-bit core available, but also an extensive range of configurable options to meet the needs of your specific application.

This two-day course, taught by MIPS Technologies engineers, will help you jump-start your design and get to market faster by giving you a basic understanding of the MIPS® architecture and the MIPS32TM 34KTM core microarchitecture.

Tailored to meet the needs of programmers and integrators, it covers all the core fundamentals, including exceptions and interrupts, MIPS16eTM code compression, instruction and data caches, configurability options, and user-defined instruction set extensions that allow you to supercharge the performance of SoC applications.

Who Should Attend

  • - Software engineers writing system level software for systems based on MIPS32 34K
  • - Hardware engineers integrating MIPS32 34K in their system
  • - Application engineers
  • - Test engineers
  • - Field application engineers
  • - Technical Marketing managers
  • - Product marketing managers

What you will learn

The focus of the class is software visible features of MIPS32 34K core, including all register states as well as the facilities for interrupt and exception processing. In addition, the student will obtain an overview of the 34K core hardware interfaces, with emphasis on functionality of the signals and present protocols. You will also learn how to take advantage of CorExtend features of MIPS32 34K core

34K Course Content

  • MIPS32 Architecture
  • MIP32 34K Core
    • CPU
    • Coprocessor 0
    • Floating Point Unit
    • Memory Management Unit
    • Exception and Interrupt Processing
    • Instruction and Data Cache Memory
    • Power Management
  • MIPS16eTM Overview
  • MIPS DSP ASE Overview
  • MIPS MT ASE Overview
  • 34K Hardware Interfaces
    • Initialization
    • OCP
    • ScratchPad RAM
    • Policy Manager
    • Inter Thread Communications
    • EJTAG
    • Memory BIST
    • COP2
  • CorExtendTM Instruction Set Extension

To schedule training:

Check the latest training schedule or send an e-mail to training@mips.com