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MIPS32® 4K® Family Architecture & Integration Training Class
Let the experts show you how to take full advantage of the 1.3 DMIPS/MHz performance, 0.25mW/MHz power consumption, and other superior features offered by the MIPS32® 4K® family of processor cores.This two-day course, taught by MIPS Technologies engineers, will help you jump-start your design and get to market faster by giving you a basic understanding of the MIPS® architecture and the MIPS32 4K core microarchitecture.
Tailored to meet the needs of programmers and integrators, it covers all the core fundamentals, including exceptions and interrupts, the MMU, instruction and data caches, hardware interface, and configurability options.
Who Should Attend
- Software engineers writing system-level software for products based on the MIPS32 4K microarchitecture
- Hardware engineers integrating MIPS32 4KE™ in their system
- Application engineers
- Test engineers
- Field application engineers
- Technical Marketing managers
- Product marketing managers
What you will learn
The class will focus on software visible features of the MIPS32 4K core, including all register states as well as the facilities for interrupt and exception processing. In addition, students will obtain an overview of the 4K core hardware interfaces, with emphasis on functionality of the signals and present protocols.4K Course Content
- MIPS32 4K Microarchitecture
- MIPS32 Architecture Overview
- MIPS32 M4K Microarchitecture Overview
- MMU - Memory Management Unit
- Exception and Interrupt Processing
- Cache Memory - Instruction & Data
- Power Management
- MIPS32 4K Core Hardware Interface
- Signal Layout
- Performance Monitoring
- Clocking and Initialization
- System Interface (BIU)
