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MIPS32® M4K™ Family Architecture & Integration Training Class
Make the most of your multi-CPU SOC design by letting the experts help you take full advantage of the superior performance density and other features of the industry's best solution for multi-CPU SOC designs, the MIPS32® M4K™ core.This two-day course, taught by MIPS Technologies engineers, will help you jump-start your design and get to market faster by giving you a basic understanding of the MIPS® architecture and the MIPS32 M4K core microarchitecture.
Tailored to meet the needs of programmers and integrators, it covers all the core fundamentals, including the MMU, SRAM interface, configurability options, and user-defined instruction set extensions for creating a highly differentiated SOC.
Who Should Attend
- Software engineers writing system-level software for products based on the MIPS32 M4K microarchitecture
- Hardware engineers integrating a MIPS32 M4K core into their system
- Application engineers
- Test engineers
- Field application engineers
- Technical marketing managers
- Product marketing managers
What you will learn
The class will focus on visible software features of the MIPS32 M4K core, including all register states as well as the facilities for interrupt and exception processing. In addition, students will obtain an overview of the M4K core's hardware interfaces, with emphasis on functionality of the signals and present protocols. You will also learn how to take advantage of CorExtend™ features of the MIPS32 M4K core.M4K Course Content
- MIPS32 Architecture
- MIPS32 M4K Core
- CPU
- Coprocessor 0
- Memory Management Unit
- Exception and Interrupt Processing
- Instruction and Data Cache Memory
- Power Management
- MIPS16e Overview
- M4K Core Hardware Interfaces
- Initialization
- SRAM Style Interface
- EJTAG
- PDTrace
- Memory BIST
- COP2
- CorExtend Instruction Set Extension
