The networking market is going through significant changes due to the drive towards open everything, smart everything, and the internet of everything. These changes place increased demand on networks in terms of the volume and speed of data handling, while also making it harder to maintain privacy and protection.
Operators are looking for rapid service deployment, plus increased infrastructure equipment lifecycle to give a higher return on investment (ROI) for a given total cost of ownership (TCO). All of this is placing pressure on OEMs to rapidly adapt to these new requirements while maintaining their differentiation and complying with new open standards.
Embedded platforms in general, and particularly in networking, by definition are based on custom solutions; some tailored by hardware and software, others purely by software. Traditionally these platforms were sold on the basis of differences in their management software and services offered. However going forward, as software defined networks (SDN) and network functions virtualization (NFV) evolve, networking OEMs must adapt to these open standards by opening their platforms to third party software vendors, or risk losing control over the associated hardware.
These changes are impacting the SoC landscape and improving the innovation cycle. SoC developers need to institute massive architectural changes to address SDN, NFV, and cloud-based initiatives, thus shifting the focus from enterprise to data centres.
Our latest MIPS Warrior IP cores offer a range of solutions for networking applications. This growing portfolio of 32-bit and 64-bit CPUs achieves new workload performance/efficiency levels. Compelling features include simultaneous multi-threading (SMT), hardware virtualization, 128-bit SIMD, advanced power management, multi-domain security, and extensibility to coherent multi-cluster operation. Building on the true 32-bit and 64-bit instruction set compatibility of MIPS, customers can easily migrate their existing 32-bit architecture to 64-bit. Warrior I-Class CPUs also include features specifically designed to address the new NFV and SDN workloads and offer the highest level of instruction per cycle (IPC) for a given silicon area.