Microchip upgrades PIC32MZ EF family to MIPS M-class M5150 MCU

Late last evening I was very excited to see an update on the Microchip Technology website announcing that the CPU at the heart of the PIC32MZ family has been upgraded to MIPS M5150, our latest Warrior M-class processor.

PIC32 is a family of high performance microcontrollers for the widest range of embedded and IoT projects. Microchip pairs the hardware with an impressive array of software and tools, including the MPLAB® Harmony software framework and low cost development tools.

The new MIPS-based Microchip PIC32MZ EF MCUs are clocked at 200MHz and provide 330 DMIPS of peak performance.

PIC32MZ EF family bloc diagram - MIPS M-class M5150 CPU_2The PIC32 EF family features a MIPS M-class CPU

Additional specifications include:

  • Memory: 16 KB I-cache and 4 KB D-cache, up to 512KB high-speed SRAM and 2 MB flash with live update
  • A fast integrated FPU for fast single- and double- precision math
  • Multiple connected peripherals with DMA: a 12-bit, 18 MSPS ADC module with up to 48 channels and 6 S&H circuits, USB 2.0 host/device/OTG, 10/100 Ethernet MAC with MII/RMII interfaces, 2 x CAN 2.0B, 6 x UART, 5 x I2C, 6 x SPI, and I2S

The new microcontrollers are designed to operate in the toughest of conditions; the rated temperature range scales from -40°C to 85°C.

MIPS M5150 highlights: high-performance DSP + FPU, full hardware virtualization

MIPS M5150 features a 5-stage pipeline based on a Harvard architecture with separate buses for instructions and data. The microcontroller-class core implements the latest MIPS32 Release 5 features, including new instructions for enhanced functionality, ultra-secure debugging, and a powerful DSP engine.

MIPS M5150 CPUMIPS M5150 provides best-in-class performance and features for microcontrollers

The MIPS M5150 processor also supports the microMIPS ISA, which contains all MIPS32 ISA instructions (except for branch-likely instructions) in a new 32-bit encoding scheme, with some of the commonly used instructions also available in 16-bit encoded format. This ISA improves code density through the additional 16-bit instructions while maintaining a performance similar to MIPS32 mode.

Finally, the MIPS M5150 microarchitecture adds an MMU with a Translation Lookaside Buffer (TLB), a unique feature among other microcontroller-class CPUs that enables software developers to run Linux-like operating systems when required.

Security is vital in embedded applications

MIPS M5150 is the first OmniShield-ready, microcontroller-class CPU to support hardware virtualization, delivering the ultimate security package for SoC designers targeting embedded and IoT applications. By using a MIPS M-class CPU, developers are able to create isolated, secure channels for remote device management and service deployment while also running an operating system like Linux required for a graphics UI.

MIPS M-class virtualizationMIPS M-class CPUs support up to seven guest operating systems

Although not certified for OmniShield, the new PIC32MZ MCUs implement several vital security features, including a crypto engine with RNG for data encryption/decryption and authentication, and advanced memory protection.

Final words

The new PIC32MZ MCUs offer a complete package for any type of embedded project, with the aim of shortening time to market and bringing better security to IoT.

The MIPS-based PIC32 family gives application developers the processing power, memory and peripherals they need to build the next amazing design.

Multiple low-cost development boards using the new PIC32MZ EF MCUs are in production with leading partners, including the new version of the Arduino-compatible Digilent chipKIT Wi-FIRE development board.

If you’re a developer interested in the new PIC32 family, follow Microchip Technology (@MicrochipTech) and Imagination (@ImaginationPR, @MIPSGuru, @MIPSdev) on Twitter to get the latest updates on these MIPS-based MCUs.

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