How to run Linux SMP in QEMU on a MIPS64 Release 6 CPU

After publishing my initial article about QEMU, many of you have sent queries about running software written for MIPS64 Release 6 CPUs (MIPS64r6) in QEMU and also about the current state of the MIPSr6 multithreading module implemented in QEMU. I decided to answer these questions in this post and turn it into a tutorial on … Read more

ELVEES goes full purple: MIPS, PowerVR and Ensigma united in one vision chip

UPDATE: ELVEES’ new ELISE SoC targeting ADAS, smart devices, IoT, augmented reality and other computer vision applications has been announced in a press release earlier this week. You can read more about the partnership between Imagination and ELVEES on our website. If you follow this blog closely (and I hope you do), you may have … Read more

PEZY licenses MIPS for “green” supercomputing

In a press release issued today PEZY Computing announced it is working on a MIPS64-based PEZY-SC2 family of many-core chips for supercomputers and HPC applications that will scale up to 4096 processing nodes. The 64-bit MIPS CPUs will act as the host processors for the system, making PEZY-SC2 the first generation of 64-bit HPC processors … Read more

Extending the MIPS Warrior CPU family

It has been a thrilling year for MIPS processors. We’ve seen exciting new designs from Loongson Technology while Cavium has introduced several OCTEON III and Fusion-M processors that cover the mid-range segment of the networking market. Multiple customers are now shipping products with Warrior CPUs, from high-end application processors to microcontrollers and embedded SoCs. Announced … Read more

QEMU: the open source MIPS64 Release 6 virtual platform

In this article I would like to present the current status of the MIPS Release 6 architecture implemented in upstream QEMU v2.4. This is one of the several major contributions from Imagination Technologies to the open source and QEMU communities in the last year. Read on to find out how MIPS Release 6 support has … Read more

MIPS in space: Inside JAXA’s Hayabusa-2 mission to asteroid rendezvous

A few days ago I brought you an exclusive interview with the New Horizons engineering team. The high-profile story presented the hardware and software systems that took the probe to Pluto and beyond. Today I’d like to revisit another important space mission called Hayabusa-2. Back in July, I wrote about the 64-bit MIPS CPU aboard … Read more

Cavium expands MIPS64-based OCTEON III family, announces design wins at ZyXEL, Xirrus

Networking specialist Cavium has announced the release of two new OCTEON III 64-bit multicore families based on the MIPS64 architecture. The press release from Cavium mentions multiple quad-core CN72XX and 16-core CN73XX parts targeting mid-range applications (networking, security, storage devices, wireless and integrated routers, etc.) that require superior compute and packet performance. Specifications include: Best … Read more

New white paper from TIRIAS Research on the world of connected devices

TIRIAS Research is a high-tech research and advisory firm consisting of a team of experienced analysts which includes Jim McGregor and Kevin Krewell. We’ve recently asked them to take a look at our newly-announced MIPS I6400 64-bit CPU and offer their impressions and thoughts on this revolutionary design in the context of today’s fast-moving computing … Read more

The latest MIPS-based communications and networking processors

A few days ago somebody asked me on Twitter for a list of MIPS-based networking processors. A few hours later I went to work and produced a list of the most recent chips that use MIPS CPUs. The list below focuses on two main categories: 32-bit home networking and 64-bit enterprise communications, storage and security. … Read more

The incredible evolution of the MIPS architecture

MIPS is the shining star of the highly efficient, low power CPU design principles that have shaped the mobile and embedded industry for nearly three decades. In this article, I will try to offer you a quick overview of how the MIPS architecture evolved from its early beginnings in the Stanford University computer science labs … Read more