We are pleased to release MIPSfpga Labs 2.0 (released July 3rd 2017). Please note that the last release was designated MIPSfpga Fundamentals v1.3.
MIPSfpga 2.0 includes a series of laboratories to acquaint you with the MIPSfpga (microAptiv) core, its memory system, and system-on-chip (SoC) design using MIPSfpga platform on the Nexys A7 (Formerly Nexys4 DDR) FPGA board. A subset of the labs (Labs 1-7 and 9) are also available for Altera’s DE2-115 board. The remaining labs could also be adapted for the Altera platform.
This material is best used in conjunction with material available in such texts as Digital Design and Computer Architecture, 2nd Edition (Harris & Harris, Elsevier, 2012). Learning the fundamentals of digital design, hardware description languages (HDLs), and computer architecture, particularly the MIPS instruction set architecture (ISA) and hardware, will lay the theoretical groundwork for completing the labs provided here.
MIPSfpga 2.0 Labs expands on the materials previously available in the MIPSfpga Fundamentals distribution by delving deeper into the microAptiv core and its memory system. By completing these labs, you will not only understand the system and core but also learn how to modify it. These labs assume that you have completed the MIPSfpga Getting Started Guide that is also available from MIPS Academic Community.
Please Register or login to download MIPSfpga Labs 2.0.