Additional Materials to teach MIPSFPGA labs

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    I am including the MIPSFPGA projects in the discussion forum part of my graduate Computer Architecture class. The school is providing Nexys4 DDR boards, bus blaster, and some additional electronics. Looking over the labs, I notice that they call out a LCD display and a buzzer. The lab it self glosses over the wiring of the hardware. Do you recommend a prototype board kit as well? The LCD is a 40 pin (20 on one side, 4 on the other) device, of which only a few pins are required. Can you tell me what other hardware should be provided? We will supply each student with the supplies for each semester.


    Nick Beser
    Johns Hopkins University



    Hi Nick,

    It´s great to hear that you are including MIPSfpga in your courses.

    In addition to the buzzer and LCD described in the MIPSfpga Fundamentals Overview document, you will need a breadboard, wires, and a few capacitors to complete the labs. If your facilities don’t already have those materials available, attached is an example bill of materials of all the hardware you need to complete the labs – including wires, breadboard, and capacitors, as well as the LCD and buzzer. The male-female jumper wires are used to connect the buzzer to the Nexys4 DDR board. The LCD mounts on the small breadboard: note that with this example bill of materials, the NC (not connected) pins of the LCD insert into the farthest most holes on the breadboard to enable wiring of the other pins. The male-male jumper wires are used to make the LCD connections. The capacitors are connected to the LCD (via the breadboard it is mounted on), as described in MIPSfpga Fundamentals Lab 8.

    You may be interested in taking a look at MIPSfpga-SOC (already available at Imagination website) and also at MIPSfpga v2.0 (planned to be released by the end of 2016). At this moment, MIPSfpga – v2.0 includes 5 new modules:
    – 1st module: It is a natural continuation of Fundamentals. It includes a lab where the student is asked to add a SPI light sensor, and also some labs about Interrupt-based I/O.
    – 2nd module: Use of the CorExtend Interface for adding User Defined Instructions (UDIs) to the core.
    – 3rd, 4th and 5th modules: Microarchitecture.
    – 3rd module: Basic instructions.
    Explanation of some basic instructions, such as an add, and, lw, beq. Proposed activities such as analyzing the forwarding unit, including new instructions, etc.
    Use of Performance Counters. Examples and exercises.
    – 4th module: The memory system.
    Cache structure. Theory and exercises.
    Cache controller. Operation of the cache controller. Exercises: analyze different policies, implement new policies, perform different code optimizations and test them with the performance counters, etc.). Cache miss management.
    Inclusion of a Scratch Pad RAM.
    Main memory and Virtual memory.
    – 5th module: Exceptions. Theory and exercises.

    Besides, after many requests, we are adding VHDL versions of the top-modules. This does not mean that we are moving away from Verilog; the soft-core will still be in Verilog, which is the language of choice for processor design.

    We´ll also add some new functionality, such as a non Bus Blaster flow.

    We are also including a guide for using MIPSfpga on Linux systems.

    Best regards
    Dani Chaver

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