- 28th March 2017 at 11:28 pm #64449
Over the last few evenings I’ve tried a few different times to walk through the MIPSfpga SoC guides to the point that I should have effectively replicated the design in Vivado 2016.2. I allowed block automation to run for the MIG 7-series, which resulted in an error about “board_if”. After a short search, it was stated on a Digilent forum that the error can be ignored since I’m using the Nexys4 DDR board definition file in my project.
When I try to validate the resulting design, I end up with an error repeated for every M_AXI to S_AXI connection between an interconnect and a given peripheral (other than the MIG) that states:
Bus Interface property FREQ_HZ does not match between [the S_AXI] and [the M_AXI at the interconnect].
Most of the solution’s I’ve found online state that the issue was related to not having a clock generator (and installing one fixes the issue). The error statement above has details stating that the slave side is at 100 MHz and the master is at 10 MHz. My clock generator seems to be configured identically to the one in the 2014.4 version of the project (I opened it in 2014.4 and used it as a reference while I worked), I’m not seeing how this could be the case.
Has anyone else seen this (even in relation to another problem)?
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