- 3rd March 2016 at 9:19 pm #64050
Hi could someone tell me why this piece of code could represent a data hazard? Im confused on the matter. Hoping someone more advanced could give some advice.
lw $5, 4($6)
sub $6, $5, $10
add $7, $6, $59th March 2016 at 10:19 pm #64052
There is no data hazard in the code the CPU is interlocked this means the the cpu will stall waiting for the lw to complete. For example if there was a cache miss on the data to be loaded the data would not be available in next cycle and the sub instruction cannot execute until it has the data so there would be a stall in the pipe line until the data was available. The pipeline only stalls when it tries to execute a dependent instruction so if there were other instructions in between the lw and sw and they did not depend on the value in $5 they would not stall.
Chris9th March 2016 at 11:10 pm #64051
I should have added hazards in most MIPS implementations only happen when reading or depending on Co-processor 0 registers so for some CP0 registers where a write to the register has just happen that changes the state of the CPU and the next instruction depends on that state you would need to add a ehb instruction (execution hazard barrier) because in this case the pipe line is not interlocked with CP0 registers (where as it is with the general purpose registers like $5) and will not stall waiting for the change of state to take effect. In the cpu programmers manual there is a list of hazards along with the number of cycles need for a change to take effect. To write portable code you should use a ehb because the cycles needed for a change to take effect can differ from processor to another
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