- 11th August 2017 at 3:28 am #64018
when I read datasheet, A brief guide to the 24K® core implementation
All 24K family cores are based on a nine-stage pipeline,(https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00355-2B-24KPRG-PRG-04.63.pdf),
but other datasheet say it is eight -stage (https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00346-2B-24K-DTS-04.00.pdf),why?11th August 2017 at 6:10 am #64021
First of all read document “MIPS32® 24K(c)f™ Processor Core Datasheet”, section “Pipeline Flow”. The section describes all stages of the pipepline. IR, Ik, IT are MIPS16e only. But in other document, section “A brief guide to the 24K® core implementation” considers IT state as an obligatory stage of the pipeline.
I think that is the reason of difference.11th August 2017 at 6:33 am #64020
Thanks for your replies!
To mips 24k,whether it support multicore through ocp I/F?
thanks11th August 2017 at 7:21 pm #64019
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