MIPSfpga – porting to Xilinx SP605 board

Home Forums MIPS Insider MIPSfpga MIPSfpga – porting to Xilinx SP605 board

This topic contains 0 replies, has 1 voice, and was last updated by  Alexander 2 years, 11 months ago.

Viewing 1 post (of 1 total)
  • Author
  • #64572


    We – ITMO University (Saint-Petersburg, Russia) – have taken part in MIPSfpga beta test program. This topic is intended to share the experience of porting the MIPSfpga project to Xilinx SP605 board with Spartan-6 XC6SLX45T device.

    Our purpose was actually getting familiar with the project to provide the students with the example of a real microarchitecture to play with. Thus, our port targeted checking the basic core functionality (we did not use pushbutton switches, JTAG, etc. at that moment). LED counting for “IncrementLEDsDelay” program depicted that the project works in general that was sufficient for our purposes.

    Overall, porting to the board was not difficult. The following sequence of steps made the project work.

    1) Creating the project. We used ISE software since Vivado seems not to support Spartan-6 devices. Adding the RTL cores.

    2) Creating the new top module with board-specific clock frequency input and the corresponding PLL unit.

    3) Generating memory. Memory was an issue here. Since the project uses on-chip memory (128 KB of reset RAM and 256 KB of main RAM), while the device has overall around 260 KB and the main RAM was not used (the program was compiled with the reset RAM), the main RAM unit was removed. Considering the reset RAM, it could not turn into BRAM units automatically (at least, in ISE software), so the options were either to use core generator or to make corrections to the Verilog RAM module. To preserve portability (at least, across Xilinx devices), we used the following directive to make the toolchain map the cores to BRAM units:

    (* ram_style = “block” *)

    The modified RAM units reside in project-specific directory (not “rtl_up”)

    4) Assigning pin constraints, compiling, loading to FPGA device.

    I don’t think that I can share the overall project (with MIPSfpga cores) freely due to the policy. Thus, I share the SP605 project only. SP605 directory has to be placed in MIPSfpga “root” directory, and “mipsfpga_sp605.v” – to “rtl_up” directory.


    Please, let me know in case you find any issues or have any recommendations.

Viewing 1 post (of 1 total)

Forums are currently locked.