- 25th March 2017 at 5:29 pm #64455
[MOVED TO MIPSfpga FORUM]
OS: Ubuntu 14.04 64-bit
I’m trying to use the project_linux as a starting point for deciding which way to go with a school project where I’ll be extending or enhancing it in some way. So far I cannot get the project through implementation.
I imported the board definitions (old/board_parts) found in master.zip and unpacked them into the board_parts of my Vivado installation. I then tried generating the bitstream for the project_linux project. It ultimately failed at implementation with 11 nets between what appear to be asynchronous resets. I do not see in the provided documentation where this is described as an expected outcome or where one has to set false constraints (or otherwise ignore) these critical warnings.
Has anyone else tried building the Linux project provided in the MIPSfpga SoC v1.0 project?26th March 2017 at 6:01 pm #64459
Small update — I let Vivado run through to generating the bitstream and was able to get equivalent results in gdb with getting the initial MIPSfpga printed to the screen as well as booting linux. It looks like to me that these false paths just need to be added to the project to quash these, if they are actually ignorable.
Edit: I now see there is a FAQ.txt stating there are critical warnings in these projects and to suggest fixes here on the forum. I don’t know how I overlooked this before. It sounds like this is all expected then. One fix, as mentioned above, is to quash the critical warnings with false path routes or some other constraint to ignore them since they’re inter-clock issues that we know about.26th March 2017 at 6:29 pm #64458
If I remember correctly, there were some warnings due to a bit width mismatch in the block ram. Those can be ignored safely. The project in the workspace/project_linux folder should synthesize to the point of generating a bitstream file despite those warnings.
Could you please share the warnings/error messages you see?
Are you synthesizing the provided project in the workspace folder? Or have you followed the documentation and created your own project?
ZubairLK26th March 2017 at 7:00 pm #64457
I started with a fresh installation of Vivado 2014.4, then installed the board_types for the Nexys 4 DDR, etc. I then opened the project and ran it through implementation. The first 4 critical warnings were about the MASTER_TYPE not matching between the blk_mem_gen0/BRAM_PORTA(OTHER) and /axi_bram_ctrl_0/BRAM_PORTA(BRAM_CTRL) (two for 0, and two more for #1). The next 11 critical warnings were things like IOFFS_GEN TX and RX which had IOB=TRUE but were not being driven by an IO element. These were flagged as invalid constraints registers. Once implementation finished, the timing was failing on 11 nets. Those nets were almost all async resets being passed around in the core (these were inter-clock routes).
Consequently, I don’t see it mentioned in the various docs that one needs to load the board files, but I would suspect they’re necessary for the sake of the constraints, etc. The projects also start up with an error if the definitions aren’t installed at the time. It might be worth adding a comment to whichever document it would be appropriate.27th March 2017 at 10:14 am #64456
Glad you managed to get it working.
Thanks for the feedback
You must be logged in to reply to this topic.