project_linux Timing Constraints

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    Last night I re-generated the bit stream from the MIPSfpga SoC project_linux xpr file. After implementation completed, the Timing Summary Report said that the design’s timing constraints were not met.

    It complained about the following inter-clock paths:

    myethrefclk to clk_pll_i     Setup -0.678ns
    myethrefclk to clk_pll_i_1 Setup -0.677 ns

    Can this safely be ignored?

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