project_linux Timing Constraints Home › Forums › MIPS Academic Forum / University › MIPSfpga discussion › project_linux Timing Constraints This topic contains 1 reply, has 2 voices, and was last updated by ZubairLK 3 years, 4 months ago. Viewing 1 post (of 1 total) Author Posts 5th June 2017 at 2:41 pm #64431 SammyParticipant Last night I re-generated the bit stream from the MIPSfpga SoC project_linux xpr file. After implementation completed, the Timing Summary Report said that the design’s timing constraints were not met. It complained about the following inter-clock paths: myethrefclk to clk_pll_i Setup -0.678ns myethrefclk to clk_pll_i_1 Setup -0.677 ns Can this safely be ignored? Author Posts Viewing 1 post (of 1 total) Forums are currently locked.