- 5th June 2017 at 2:41 pm #64431
Last night I re-generated the bit stream from the MIPSfpga SoC project_linux xpr file. After implementation completed, the Timing Summary Report said that the design’s timing constraints were not met.
It complained about the following inter-clock paths:
myethrefclk to clk_pll_i Setup -0.678ns myethrefclk to clk_pll_i_1 Setup -0.677 ns
Can this safely be ignored?6th June 2017 at 10:40 am #64432
Some history from memory…
While developing MIPSfpga SoC, I found that Ethernet would sometimes glitch.
A packet lost here and there. A TCP connection dropped. I tried debugging it in detail a few times but couldn’t trace the source of the problem (I was looking from a SW/Linux angle. And not RTL). If I’m not mistaken, I thought I documented this in some appendix/faq.
As MIPSfpga SoC wasn’t intended as a production platform but a teaching resource. Despite the occasional glitch, the Ethernet part of MIPSfpga SoC was sufficient to showcase how a complex IP -> AXI -> AHB-Lite -> MIPS -> Linux Kernel -> Linux Userspace path worked.
There were some timing constraint issues on the MIPSfpga SoC project_linux. When I stared at them, I found them to be with areset wires which I ignored and then subsequently forgot about. Could they be linked with occasional Ethernet glitch. Possibly. Not sure.
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