- 25th July 2017 at 10:55 pm #64423
Hello! This short document contains some information about running Linux on MIPSfpga-plus system that is deployed on Terasic DE10-Lite development board with Altera MAX10 chip and SDRAM:
https://github.com/zhelnio/memos/tree/master/public/04_mips_linux26th July 2017 at 11:24 am #64425
Very good work indeed!
Regarding the ahb-lite uart + ahb-lite sdram wrapper. AFAICT, they are written in Verilog. Is it ‘technically’ easy to port to an equivalent Xilinx FPGA based board? Is there a board with 32/64Mbyte SDRAM with an easy interface to hook up to.
MIPSfpga-SOC (not mipsfpga-plus) is based on Xilinx only and uses an AHB-lite -> AXI bridge to use Xilinx IP blocks.26th July 2017 at 5:43 pm #64424
Thanks for your kind words! Yes, UART and SDRAM modules of MIPSfpga-plus are platform independent. They are written on pure Verilog. So there should be no problem with porting this configuration to Xilinx boards. The only thing you have to check (and may be configure) are SDRAM timings and clock shift. The current version of SDRAM module supports only x16 memory, but this can be easily fixed.
Sorry, but I cant help you with information about Xilinx FPGA based board with SDRAM chip on it. Because I have only Altera FPGA based boards.20th January 2018 at 8:39 pm #89100
Awesome! I would definitely try this!
My question is: if sdram and uart controller are pure verilog code independent of Altera avalon bus, it is not quite easy for adding more peripherals to this system. Is it possible to program a “ahb-lite to avalon” bridge module so that we could use the many IPs inside the Qsys to build a more powerful linux system.
Forums are currently locked.