Running MIPSfpga on a BASYS-3 board

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This topic contains 4 replies, has 1 voice, and was last updated by  Jay Ng 1 year, 5 months ago.

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  • #115198

    Jay Ng
    Participant

    Question from a user of MIPSfpga:

    I was trying to follow the videos (Module 4) to create a Vivado project using MIPS FPGA.
    I am targeting BASYS-3 board but it looks like the design uses more LUTs than that available on BASYS-3.
    It generates error when I try to generate bitstream.

    I do see that you have provided files for BASYS-3 so I was wondering if I would be able to create a working project with BASYS-3 or do I have to use NEXYS-4 DDR board.

    Answer:
    You can run all the Labs on a Basys-3. You need to change the configuration files.
    – There are examples in the Labs under “Porting to other boards”.
    https://www.youtube.com/watch?v=fVee3JuugYY
    – There’s also a section at the end of the video by Sarah Harris at Harvey Mudd in 2015.
    https://www.youtube.com/watch?v=Xii1q76goZM&list=PLSTiCUiN_BoJcWlxQTxbKE3VQBQhwFLDP&index=14

    You need a Nexys 4 DDR board for the SoC exercise because this needs more memory.

    But all the Labs (all 25) can run on Basys 3.

    #115199

    Jay Ng
    Participant

    User:
    I tried what the video said and it still gives me Implementation errors stating that LUT is over utilized.

    Answer:
    Have you looked at Section 3 of Lab 1 of MIPSfpga-Labs (attached)? It may provide some more details than the video.
    From the messages that you get, I think that the main problem is that the target device has not enough LUTs for your design. This may be related with the required reduction in memory size, as the document explains.

    #115200

    Jay Ng
    Participant

    User:
    I was able to fix the issue of overutilized LUT in BASYS-3 project.
    There are 2 instances of the same Verilog constant file that gets added into the project.
    I don’t know why. I could not remove one instance from the project.

    I had to reduce memory size in both the files and I was able to generate bit stream.

    However, there was another problem that happens no matter which FPGA board I use (Basys-3 or Nexys-4 DDR).
    I have attached the WARNING message.
    Looks like it cannot find any memory (RAM) files which holds the instruction.
    So when I download the program on the board and press the reset button, nothing happens as it does not find memory from where it can run the instructions.

    Answer:
    If you follow the exact steps explained in Lab 1 of MIPSfpga-Labs (attached) for creating and compiling your Vivado Project, you will be initializing the MIPSfpga memory with a program that makes the LEDs display increasingly incremented values. In that case, when you press reset button, the program should start running.
    You can find the Verilog files where the reset RAM and the Code/Data RAM are implemented and initialized in folder “rtl_up\system\memories”. Open, for example, file ram_b0.txt, to see the initial program stored in memory.
    From the Warning that you get, it looks like you have not added correctly these files. Be especially careful with the steps where you have to add the Verilog sources to your project (Figures 3-5 in the attached document).

    #115201

    Jay Ng
    Participant

    User:
    I followed the following steps:

    Added files while creating the project, created a clock divider, set testbench.v as top-level simulation file, added memory files from LED_DELAY folder as simulation source files, simulated the design.
    Then generated the BIT file. and it worked.

    But for my project I have 2 instances of MEMORY files (first instance when I added files while creating project) and (second instance when I added them as simulation files).

    Now which instance is used?

    Also, do I have to simulate the design first and then generate BIT FILE?

    Answer:
    Great that it is working now!
    – Simulation is not required at all: after performing Section 1, you can completely skip section 2, and still Sections 3 and 4 will work perfectly.
    – For generating the bitstream, Vivado uses the instance that you included in the Design Sources; for simulating, Vivado uses the instance that you included in the Simulation Sources. Please, look at the attached figure. In fact, the two sets of memory files are not equal: the one used for generating the bitstream includes a delay not included for simulation.

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    #115203

    Jay Ng
    Participant

    User:
    I followed the following steps:

    Added files while creating the project, created a clock divider, set testbench.v as top-level simulation file, added memory files from LED_DELAY folder as simulation source files, simulated the design.
    Then generated the BIT file. and it worked.

    But for my project I have 2 instances of MEMORY files (first instance when I added files while creating project) and (second instance when I added them as simulation files).

    Now which instance is used?

    Also, do I have to simulate the design first and then generate BIT FILE?

    Answer:
    Great that it is working now!
    – Simulation is not required at all: after performing Section 1, you can completely skip section 2, and still Sections 3 and 4 will work perfectly.
    – For generating the bitstream, Vivado uses the instance that you included in the Design Sources; for simulating, Vivado uses the instance that you included in the Simulation Sources. Please, look at the attached figure. In fact, the two sets of memory files are not equal: the one used for generating the bitstream includes a delay not included for simulation.

    Attachments:
    You must be logged in to view attached files.
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