sdram support

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    Hello! I have added sdram chip support to project (mfp_ahb_ram_sdram module).
    It was successfully tested on Terasic DE10-Lite board and can be ported to other boards.

    Supported boards:
    – Terasic DE10-Lite

    Main features:
    – sdram access module is very small (about 300 rows);
    – only x16 sdram DQ width is supported;
    – only main operations are supported (init, read, write and auto-refresh);
    – page (burst) memory access is not supported;
    – cpu clock is used to run sdram access module (no clock domain crossing);
    – it is easy tunable: all time constraints are coded as module params;
    – Micron Technology, Inc. (“MTI”) SDRAM Verilog model (v2.3) is used for simulation;
    – all code is simulated with modelsim and tested on Terasic DE10-Lite board;
    – 04_memtest program added – it writes a big array to memory, flushes cache and then read it after delay. The program displays the current step on LED. 7-segment indicator shows information about current iteration and error count.
    – there is a separate sandbox, where I have developed this sdram access module: It contains some testbenches and standalone hardware tests. This project includes AHB-Lite master, that works without cpu. It can be used to port sdram support to other boards.
    – MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX is not supported with sdram;
    – PLL ip core have to be added to board top level code to provide fixed memory clock shift;

    04_memtest program run order
    – select data memory type (variant) in mfp_ahb_lite_matrix_config.vh
    MFP_USE_BYTE_MEMORY – fpga block RAM with byte storage (x8);
    MFP_USE_WORD_MEMORY – fpga block RAM with word storage (x32);
    MFP_USE_BUSY_MEMORY – fpga block RAM with busy imitation (it sets HREADY after some tunable delay)
    MFP_USE_SDRAM_MEMORY – sdram memory
    – set memory settings in main.c (according to previous step)
    – set stack size in 02_compile_and_link.bat;
    – build the rtl code and program the board;
    – press reset button on the board to provide sdram initialization;
    – build the software and upload it to the board:
    – LED description:
    0 – write;
    1- cache flush;
    2 – delay;
    3 – reading and checking;
    4 – finished, no errors found;
    5 – finished with errors.
    – HEX description (de10-lite have 6 of it): CCEEEE
    CC – read iteration number;
    EEEE – errors count;

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