Utilizing all 4 exposed uart's

[scottParticipant]

Hi. I’m trying to use the 4 exposed UART’s on the creator ci20 v2 board.

I got UART0 working fine.
After I removed the agetty service for ttys4, UART4 is working fine.

I can’t get either UART1 or UART3 to work on loopback.

I configure all of the Uarts as
ttys -F /dev/ttySx raw
ttys -F /dev/ttySx 9600
ttys -F /dev/ttySx -echo -echoe -echok

then I connect their respective rx pin to the tx pin and run.
cat /dev/ttySx &
echo “hello” > /devttySx

As I mentioned. I see the Hello using 0 and 4, but not 1 or 3.

Also I’ve tried doing a loopback on gpio
when I echo 1 > gpio[whatever the tx pin#is]
I read back a 1 when I cat gpio[whatever the rx pin#is]

So the hardware seems fine.
Is there some service hogging the uart’s I want?

[ZubairLKParticipant]

Hi Scott,

Welcome to the Creator forums.

pinmuxing would be the obvious culprit.
Are you using kernel 3.0.8 or 3.18?

In 3.18, I think the pinmux hasn’t been defined for UART 1

https://github.com/MIPS/CI20_linux/blob/ci20-v3.18/arch/mips/boot/dts/jz4780.dtsi#L450

But UART3 should work. Unless u-boot is perhaps configuring uart0/uart4 correctly. And something is missing in the uart1/3 driver side..

Which brings the question again. which kernel are you working on?

Regards,
ZubairLK

[scottParticipant]

Thanks for the reply.

I believe I’m using the 3.18 kernel as this was with the Debian 8 2015-09-09 Beta image.
I will give UART3 another attempt to make certain.

I remember seeing, in the uboot code, setup for UART 0 & 4. Then some setup for UART 3 as JTAG.

I wondered if the JTAG could be preventing me from using the pins. I seem to remember that if the JTAG is enabled on the pic32, all pin remapping and control gets ignored on those pins. I wasn’t sure if it was the same for the JZ4780.

[harveyhuntParticipant]

Hi Scott,

I have got all of the UARTs working on the board, aside from UART 3 (more on that later).

I’ve made some changes to device tree, you can find the fix on this branch: https://github.com/HarveyHunt/CI20_linux/tree/ci20-v3.18-enable-uarts

Or as a patch here: https://github.com/HarveyHunt/CI20_linux/commit/c39b918cb3bc51f83b18ce1c2ad4523f1fd6904e.patch

You’ll need to recompile your kernel with my fix applied.

UART 3 is trickier as it is on the same pins as EJTAG. There are some GPIO registers in the SoC that need setting, most likely from U-BOOT. Unfortunately the UART 3 GPIO doesn’t come out on any other pins, so I can’t give you a workaround for it.

I’ll continue working on UART 3 and keep you posted. 🙂

[scottParticipant]

Thank you very much for this effort.
I could definitely see not putting the uart3 changes in anything mainline.

The project I’m working on for my company would benefit from using all 4 even if sacrificing jtag abilities.
Though in the long run it would be temporary since part of this is to eliminate boards with low cost MCU’s with one SOC. This would of course free up the UARTS that were being used to talk to these boards.

[harveyhuntParticipant]

Hi Scott,

Good news – I have got UART3 working and also updated the eLinux wiki with the details.

The original patch I sent you has been merged into the Ci20 kernel [0], so will be included in the next image release. Until then, you’ll need to compile the kernel yourself, using the linked github repository.

The instructions for enabling UART3 are now on the wiki [1], you will need to recompile UBOOT. All of the steps are detailed on the eLinux page.

Harvey

[0] https://github.com/MIPS/CI20_linux/pull/73
[1] http://elinux.org/CI20_Hardware#Using_UART3

[scottParticipant]

Thanks again for working this out.

[GeneParticipant]

In my projects the UARTs working on the board, aside from UART 3.
According to me you need to recompile your kernel with my fix applied.
UART 3 is trickier as it is on the same pins as EJTAG. There are some GPIO registers in the SoC that need setting, most likely from U-BOOT.
Unfortunately the UART 3 GPIO doesn’t come out on any other pins, so I can’t give you a workaround for it.

[Author]

Posts