Sammy

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  • in reply to: Building the MIPSfpga SoC "project_linux" from scratch #64450

    Sammy
    Participant

    I would definitely be interested in your paper. Would you mind sending it over to sammy.lin@alum.rit.edu?

    in reply to: Byte Write Enable in Block Memory Generator? #64439

    Sammy
    Participant

    I’ve added the MIG and DDR to my design and went ahead and loaded the following test:

    int main() {
        volatile unsigned char buffer[10];
        volatile int i = 0;
    	while(1) {
                buffer[i++] = 0x09;
    	}
    
      return 0;
    }

    I changed the linker script and fpga.h to put code and the stack to 0xa0001000 and 0xa0004000 respectively. When I step through the code, I get the following:

    2: x/12i $pc
    => 0xa000101c <main+28>:	sb	a0,0(v0)
       0xa0001020 <main+32>:	b	0xa000100c <main+12>
       0xa0001024 <main+36>:	nop
    

    As I step through the iterations of the store byte instruction, I get the following for the contents of $v0:

    (gdb) x 0xa0003fd8
    0xa0003fd8:	0x00000009
    …
    (gdb) x  0xa0003fd8
    0xa0003fd8:	0x00000900
    …
    (gdb) x 0xa0003fd8
    0xa0003fd8:	0x00090000

    I was kind of expecting it to fill it with all 0x09s e.g.: 0x09090909
    Is this behavior expected?


    Sammy
    Participant

    Hi,how many gates it will take up in asic?

    Is this a hypothetical question? Correct me if I’m wrong, I thought the license does not permit putting MIPSfpga on silicon.

    in reply to: Building the MIPSfpga SoC "project_linux" from scratch #64452

    Sammy
    Participant

    Hi Thomas. I’m about to migrate to a newer version of Vivado myself and was wondering if the warnings about async reset between MIG and HRESETn is still an issue.

    Also, in your other post you mentioned you updated the MIPSfpga RTL. Did you use MIPSfpga-plus?

    Looking forward to your response and thanks for all your contributions so far.

    in reply to: Byte Write Enable in Block Memory Generator? #64441

    Sammy
    Participant

    Thanks, Zubair. I was just looking at section 6.3 of the appendix.

    When I add in the MIG and DDR, byte writes should be OK?

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