Nicholas

Forum Replies Created

Viewing 8 posts - 1 through 8 (of 8 total)
  • Author
    Posts
  • in reply to: Problems getting BusBlaster running #64502

    Nicholas
    Participant

    Bruce, executing the loadMIPSfpga, and then repeatively running the load command, I got it load the code onto the Nexys4_DDR board. I think I had to send it about 10 times before it worked.

    Nick

    in reply to: Problems getting BusBlaster running #64503

    Nicholas
    Participant

    Bruce, can you expand on your comment? I tried to run the loadmipsfpga.bat without opening the two windows, but did not have any luck. Can you post a new bat file that does what you suggest?

    Thank-you,

    Nick


    Nicholas
    Participant

    Enrique,

    Thank-you for your reply. While I did earlier remove Vivado 2015.4, I had not touched Vivado 2014.4. I did notice something else. Out of desperation, I added a USB hub, and saw that the USB Serial Converter A and USB Serial Converter B had reappeared. I was able to download the MIPSfpga.bit file to the Nexys 4.

    I think I will do what you suggest, and since Vivado 2016.1 has come out, remove the older versions, and then load that. I will let you know if I run into issues with the newer version.

    I am still having problems with the Bus Blaster. Can you recommend who I might contact to get some assistance with it?

    Nick

    in reply to: Problems getting BusBlaster running #64505

    Nicholas
    Participant

    The system posted the message without allowing me to include the third screenshot (third command window from loadMIPSfpga.bat.
    Nick

    in reply to: FAQ: How to Register IUP and Get Access to the Materials #65460

    Nicholas
    Participant

    I have had access to the MIPSfpga materials and the MIPSfpga SOC, however I see that new releases have come out, and there does not appear to be a way of accessing them short of asking for permission all over again. I am currently using MIPSfpga materials for my graduate level computer architecture class at Johns Hopkins University. I would like to access the latest versions.

    I am also having problems getting the Bus Blaster working with the Nexys4 DDR board, and would like to get an email contact of someone who can offer advice to get around the problem.

    My email address is: nbeser1@jhu.edu

    Thank-you,

    Nick

    in reply to: FAQ: Find the right Vivado License for MIPSfpga #64508

    Nicholas
    Participant

    Enrique,

    Thank-you for your fast reply. Unfortunately, I am following the directions in Lab02 exactly, and my directory structure is setup exactly as you have suggested (no spaces). I am going to put the output from the loadMIPSfpga.bat script after this message, and maybe it might suggest a cause. I am curious about one other point. The Nexys4_DDR board is loaded with the MIPSfpga code first, and it is connected with it’s own USB cable. I then plug in the busblaster connection, and then connect my second USB cable to the bus blaster. The instructions don’t give a diagram that show that type of connection, but the Nexys4 board has to be connected inorder to save the code.

    Is that the correct configuration? The instructions only mention connecting the BusBlaster via the USB cable.

    Here is the log from the two cmd windows:
    Open On-Chip Debugger 0.9.1-dev-microAptiv-dirty (2015-05-08-15:32)
    Licensed under GNU GPL v2
    For bug reports, read
    http://openocd.sourceforge.net/doc/doxygen/bugs.html
    adapter speed: 15000 kHz
    adapter_nsrst_delay: 100
    trst_and_srst separate srst_gates_jtag trst_open_drain srst_open_drain connect_d
    eassert_srst
    Change MIPS Bus Blaster Default Adapter speed
    adapter speed: 14000 kHz
    scan delay: 20000 nsec
    running in fast queued mode
    Info : clock speed 14000 kHz
    Info : JTAG tap: mAUP.cpu tap/device found: 0x00000001 (mfg: 0x000, part: 0x0000
    , ver: 0x0)
    Info : accepting ‘gdb’ connection on tcp/3333
    Warn : target not halted
    Info : JTAG tap: mAUP.cpu tap/device found: 0x00000001 (mfg: 0x000, part: 0x0000
    , ver: 0x0)
    Error: timed out while waiting for target halted
    TARGET: mAUP.cpu – Not halted
    in procedure ‘reset’
    in procedure ‘ocd_bouncer’

    in procedure ‘reset’
    Warn : target not halted
    Warn : target not halted
    Info : Halt timed out, wake up GDB.

    Second window:
    Reading symbols from FPGA_Ram.elf…done.
    0x00000000 in ?? ()
    The target is assumed to be little endian
    JTAG tap: mAUP.cpu tap/device found: 0x00000001 (mfg: 0x000, part: 0x0000, ver:
    0x0)
    timed out while waiting for target halted
    TARGET: mAUP.cpu – Not halted
    in procedure ‘reset’
    in procedure ‘ocd_bouncer’

    in procedure ‘reset’
    Loading section .exception_vector, size 0x320 lma 0x80000000
    Loading section .text, size 0x16ec lma 0x80000320
    C:MIPSfpga_FundamentalsScriptsNexys4_DDR..startup.txt:4: Error in sourced c
    ommand file:
    Load failed
    (gdb)

    in reply to: FAQ: Find the right Vivado License for MIPSfpga #64510

    Nicholas
    Participant

    Laurence,

    Can you confirm that the only Vivado version that will run MIPSfpga (not just MIPSfpga SoC) is 2014.4? I have a 64 bit windows 10 system, with a Nexys 4 DDR and the Bus Blaster with the Codescape Software Development Kit.. While I can load code into the Nexys 4 system, I am not able to get it to single step and halt at break points. I have tried both 2014.4 and 2015.4. I am looking for solutions to get single step and break points working.

    Thank-you,
    Nick

    in reply to: MIPSfpga SoC: Advanced Starter Tutorial #64551

    Nicholas
    Participant

    Request access to MIPSfpga SoC

    I am a instructor at the Johns Hopkins University teaching a graduate level computer architecture class (525.412). I am currently converting the class to the Sarah Harris’s text, and would like to have my graduate students do some advanced projects based on MIPSfpga. Please give me permission to access the beta files to determine the suitability for my graduate class.

    Thank-you,

    Dr. Nicholas Beser
    email: nbeser1@jhu.edu

Viewing 8 posts - 1 through 8 (of 8 total)