Forum Replies Created
- 25th July 2017 at 10:48 am in reply to: Codescape GNU Tools for MIPS.MIPS HAL.Interrupt handlers and the M5150 core #64023
Sure, sorry about that copy and paste error.
Thanks for re-posting.
Sean.24th July 2017 at 12:43 pm in reply to: Codescape GNU Tools for MIPS.MIPS HAL.Interrupt handlers and the M5150 core #64025
The compiler generated interrupt handler logic in the HAL currently does not offer support for the MCU ASE vectored interrupt extension, so it only supports up to HW5. The two highest priority MCU handlers can still be used, but the compiler generate code will not automatically disable the lower priority interrupts. Using the following attributes will allow you to use C generated interrupt handlers for HW6 and HW7:
void __attribute__ ((interrupt(“vector”), keep_interrupts_masked)) _mips_isr_hw6();
For HW6 it will not allow HW7 to nest during executions of the HW6 handler. To unmask HW7 during HW6 handling, the C code would need to preserve EPC and STATUS then update the STATUS register to clear HW6 to SW0 and enable the IE bit. Before returning it would also need to restore EPC and STATUS.
It is also necessary to build a custom version of the mips_excpt_isr.S file. You can find a template in share/mips/hal/mips_excpt_isr.S. Copy this to your project and amend the end of the file to add the text in bold below otherwise the additional HW interrupt entry points will not be located correctly. Build this file with the same options as the rest of your project and ensure it is included in the link by specifying it directly on the command line as a .o file (rather than within an archive).
Inspecting the command line, it looks like you have used -Im <india, mike>.
Please try again with -lm <lima, mike>.
See https://en.wikipedia.org/wiki/NATO_phonetic_alphabet for india, mike and lima referances.
As discussed, this [-lm] is to force libm to be linked, in some cases it is not implicitly used at link time.
Sean.25th November 2015 at 9:35 am in reply to: MIPS MicroAptiv Nexys4 DDR Implementation: Boot Loader #64540
I’ve moved your conversation to the MIPS FPGA specific topic an asked one of my colleagues who is more familiar with the MIPS FPGA project to take a look.
Sean.24th November 2015 at 2:11 pm in reply to: MIPS MicroAptiv Nexys4 DDR Implementation: Boot Loader #64542
Is this the MIPS FPGA project that you are working on?
I’m not clear what you are trying to do when you say “environment in which I can incorporate the whole GCC toolchain?”. Please could you explain what you want to achieve here? Do you mean an IDE which incorporates the GCC toolchain for MIPS?
This is not an JTAG probe Imagination support so sorry but we do not have information about this device. You might like to try Compex support, or their manuals. The WPJ344 board manual (http://www.compex.com.sg:809/DownLoads/Manual/PCBA-WPJ344_HW_Manual.pdf) suggests OCD Commander ver2.5.4 in their JTAG procedure.
Sorry I can’t be of more assistance.
Great to hear you are taking a look at this. You will have a steep learning curve if this is your first venture into a compiler so a suggestion is to focus on a few smaller details and expand from there.
The MIPS compiler is built on the open source GCC framework and as such the vast majority of the process of compiling code is not MIPS specific. The best starting point for this is the GCC project website http://gcc.gnu.org and for information on the internals of GCC: https://gcc.gnu.org/onlinedocs/gccint/
The GCC project has both a general user help mailing list and a developer mailing list which would be a good place to post any more specific questions you have. There will be MIPS developers on those lists if there is something specific about MIPS you need some pointers about. That said, in general the source of GNU projects is intended to be self-documenting and following through various passes in the compiler should be possible.
If you have questions about the code which we have in our Codescape GCC toolchain release that is not already in the repository hosted by gcc.gnu.org then feel free to ask here.
Sean.22nd July 2015 at 2:58 pm in reply to: Warning: MIPS32 Rev 2 instruction is not implemented. Instruction ignored #64080
What arguments are you providing to GCC? By default mips-mti-elf-gcc will generate MIPS32R2 instructions.
SEB (Sign-Extend Byte) instruction does not look like it is defined in the instruction spim is designed to work with (a much older MIPS instruction set).
Have a look at the MIPS GCC options for targeting different architectures or use a more up-to-date simulator/emulator (i.e. QEMU) depending on what you are attempting to achieve.
I believe you already have a solution to this via Partner Portal.
Just to update this ticket, PIE executables can now be debugged with binutils and glibc support is committed to upstream repos:
binutils in binutils-gdb: a5499fa Add support for DT_MIPS_RLD_MAP_REL.
glibc: a2057c9 Add support for DT_MIPS_RLD_MAP_REL.
The GDB update is currently pending review.
This fix be generally available in the 2015.06 series tools due to be released later this year but to use it you have to have the GLIBC installed from this set of tools.
Sean.1st July 2015 at 2:49 pm in reply to: Navigator Console’s tkcon shows empty window when running a script #64111
Navigator software uses a 32bit Java Virtual Machine. Ubuntu x64 does not, by default, get installed with all the required 32bit compatibility libraries. You may be missing these 32 bit supporting libraries.
Please follow this guide for details of how to install them.
There are additional libs you may have to install but try that first and let me know if it resolves your issue.
The default boot exception vector is 0xBFC0 0000 which is where the CPU will start fetching instructions at power up or reset.
There are numerous docs available online but I suggest you have a look at our Training Material, specifically Memory Map starting at 4:15.
Sorry for the delay in getting back to you.
Maybe you could share your test.c with us if you think that may be the issue?
However … it doesn’t sound like the code is the issue. Can I confirm that you have downloaded and unpacked one of the Codescape GNU tools tar files? Please also confirm you have not re-located/moved any files from the structure that was unpacked? The mips-mti-elf-gcc.exe application uses the other applications and libraries that were unpacked and is not expected to run in isolation.
The setup we recommend (and what is provided by the Codescape MIPS SDK Essentials installer) is to append the bin directory that was unpacked to the PATH (instructions here) and then in any console window you can type:
C:Usersseanimgtecexampleshello>mips-mti-elf-gcc.exe -S hello.c
I can confirm the command you are using is correct, so it sounds like something is wrong with your setup. If something was wrong with the C file, the tools would generate an error.
Sean.19th February 2015 at 9:58 am in reply to: Codescape MIPS SDK / proSDK cycle accurate instruction set simulator/emulator #64114
The Codescape MIPS SDK is not intended to support the capability to provide precise H/W performance information other than via H/W emulated, FPGA or real target platforms. I am sorry for leading you in the wrong direction if QEMU is not capable of providing the measurements you require.
Is there a reason you cannot use hardware to achieve this measurement? There are a number of 24K based platforms available fairly cheaply, Ubiquiti RouterStation for example.
Sean.17th February 2015 at 10:26 am in reply to: Codescape MIPS SDK / proSDK cycle accurate instruction set simulator/emulator #64116
Ok, thanks for letting me know. I’ll be honest – I’ve never actually used the CP0.count registers on QEMU, only on real hardware.
In QEMU the calculation is based on internal QEMU timers. It’s not immediately clear why returned values differ so much.
What you can do however is to enable virtual instruction counter on QEMU to get reproducible results, for example “-icount auto”:
enable virtual instruction counter with 2^N clock ticks per
instruction and enable aligning the host and virtual clocks
I’m afraid I’m not able to test this at the moment – would you be give it a go and let me know if this gives you the results you need?
Sean.16th February 2015 at 1:15 pm in reply to: Codescape MIPS SDK / proSDK cycle accurate instruction set simulator/emulator #64118
The Codescape MIPS Essentials SDK provides QEMU emulator giving an instruction accurate simulator. You can use the count registers in order to count the number of cycles (i.e. sample at beginning/end and take the difference).
The GCC toolchain provided has a number of MIPS specific headers to assist you in accessing this register. include mips/cpu.h and use the function mips_getcount()
Please be aware that this register wraps every 0xFFFFFFFF instructions. In order to detect this wrap you would need to develop additional code to handle using interrupts.
Hope that helps?