MIPS in the Media

MIPS is using an FPGA platform from Siemens Digital Industries Software to accelerate software development for its eVocore P8700 RISC-V multiprocessor....

Even though the company had telegraphed its big move, MIPS’s adoption of the RISC-V ISA for its future processor cores hit me like a ton of bricks. ...

MIPS announced that Mobileye adopted its eVocore P8700 for the next-generation EyeQ SoC for autonomous driving and advanced driver assistance systems (ADAS)....

MIPS has announced the availability of the eVocore P8700, the industry’s highest-performance, most scalable RISC-V multiprocessor IP. The P8700 has already been licensed for applications including a...

MIPS has developed its first licensable CPUs implementing the RISC-V instruction set by repurposing older MIPS-compatible cores. The P8700 and I8500 outperform most other RISC-V designs....

MIPS, a developer of scalable RISC processor IP, has announced the availability of the eVocore P8700, said to be the industry’s highest performance, most scalable RISC-V multiprocessor IP....

RISC-V is everywhere. RISC-V is redefining computing. And that's not just for this quarter. This is for the next era of computing. ...

Perhaps the biggest news at the RISC-V Summit came from MIPS. The story of MIPS is as full of twists, turns, and surprises as any you get in Silicon Valley....

Members across the ecosystem have continued to innovate with cutting-edge RISC-V hardware and software solutions. MIPS announced the availability of its first RISC-V IP core, the high performance and ...

With its transition to RISC-V, MIPS is targeting the high-performance segment of the processor market, leveraging its differentiation in real-time features...

MIPS is showing the first results of its pivot to the RISC-V architecture following the collapse of Wave Computing....

MIPS, a developer of RISC processor IP, is entering into the RISC-V market and has offered previews of its first products in its eVocore product line-up. ...

MIPS is dead, right? Well, there’s now very little done on the architecture itself, MIPS (the company) has decided to switch to RISC-V architecture, and unveiled the eVocore product lineup currently...

SAN JOSE, Calif., May 10, 2022 — MIPS, a leading developer of highly scalable RISC processor IP, announces its entrance to the RISC-V market, previewing the first products in its eVocore product lin...

MIPS Tech is no longer working on their MIPS CPU instruction set architecture but has been taking on RISC-V based designs. Today the company made the bold announcement for their new eVocore P8700 and ...

MIPS Tech is now not engaged on their MIPS CPU instruction set structure however has been taking up RISC-V based mostly designs. At this time the corporate made the daring announcement for his or her ...