ChrisImgtec

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  • #64034

    ChrisImgtec
    Moderator

    The designers said the right thing to do for this version of the processor is ehb or nop or another instruction between the wrpgpr and access to srsctl.

    Chris

    #64036

    ChrisImgtec
    Moderator

    Hi Petko,

    Sorry for not getting back to you sooner I had some thinking to do about this and it does seem strange. I’m reaching out to the designers and will get back to you.

    Chris

    #64044

    ChrisImgtec
    Moderator

    I guess the documentation wasn’t updated to reflect that the sample application can now be found in the libapi directory of the yamon source gzip file on the same web page.

    https://community.imgtec.com/downloads/yamon-version-02-22-source-file-only

    #64059

    ChrisImgtec
    Moderator

    Netlogic can add instructions to the MIPS instruction set for the processors so you would need to contact them for more information

    #64048

    ChrisImgtec
    Moderator

    If there is a branch to the branch instead of the li then the code would add a 1 to what ever is in v0 at the time.

    #64038

    ChrisImgtec
    Moderator

    It is documented in the software users manual:

    https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00934-2B-microAptivUC-SUM-01.03.pdf

    See Table 2.9 Execution Hazards

    #64031

    ChrisImgtec
    Moderator

    It’s not like Intel. There are videos that tell you how. Use the following link and select the “TLB” video.
    https://community.imgtec.com/developers/mips/resources/training-courses/mips-basic-training-course/

    #64051

    ChrisImgtec
    Moderator

    I should have added hazards in most MIPS implementations only happen when reading or depending on Co-processor 0 registers so for some CP0 registers where a write to the register has just happen that changes the state of the CPU and the next instruction depends on that state you would need to add a ehb instruction (execution hazard barrier) because in this case the pipe line is not interlocked with CP0 registers (where as it is with the general purpose registers like $5) and will not stall waiting for the change of state to take effect. In the cpu programmers manual there is a list of hazards along with the number of cycles need for a change to take effect. To write portable code you should use a ehb because the cycles needed for a change to take effect can differ from processor to another

    #64052

    ChrisImgtec
    Moderator

    Hi Author,

    There is no data hazard in the code the CPU is interlocked this means the the cpu will stall waiting for the lw to complete. For example if there was a cache miss on the data to be loaded the data would not be available in next cycle and the sub instruction cannot execute until it has the data so there would be a stall in the pipe line until the data was available. The pipeline only stalls when it tries to execute a dependent instruction so if there were other instructions in between the lw and sw and they did not depend on the value in $5 they would not stall.

    Chris

    #64630

    ChrisImgtec
    Moderator

    On Linux you would have to write a module and then call it from your program.

    #64632

    ChrisImgtec
    Moderator

    The Software User’s Manual for the core or chip you are using should have the information on the performance counters. Note not all core support performance counters. The performance counters can only be accessed on Kernel mode.

    #64587

    ChrisImgtec
    Moderator

    Here’s one I use:

    #define setsr(x)
    ({ unsigned int X;
    X=x;
    __asm__ __volatile (“mtc0 %0, $%1, 0” : : “d” (X), “i” (C0_STATUS));})

    #64585

    ChrisImgtec
    Moderator

    Hi,

    It should work. Did you set the ITC up on each core? Each core must be set up individually.

    #64073

    ChrisImgtec
    Moderator

    Sorry should have said: Imagination builds the Chromium browser on a regular basis

    #64074

    ChrisImgtec
    Moderator

    Imagination the Chromium browser on a regular basis. I’ll check with our Linux team and get back to you on the Debian support. (All are crossed compiled).

Viewing 15 posts - 1 through 15 (of 68 total)