Forum Replies Created
3rd August 2015 at 7:57 pm #64076
Support is not directly available through Imagination for release 2. You can still try to ask questions, see http://www.gnu.org/help/gethelp.en.html. release 4 was short lived and not a widely used release so you shouldn’t need support for it.
Chris1st July 2015 at 9:36 pm #64100
do you use 0x to indicate it’s hex?1st July 2015 at 9:30 pm #64109
Check the Global Interrupt Controller Status Register (GCR_GIC_STATUS at GCR base + Offset 0x00D0). If bit 0 is set then you have a GIC.
Check the Global Interrupt Controller Base Address Register (GCR_GIC_BASE at GCR base + Offset 0x0080). Bit 0 should be set to 1 if the GIC is enabled.1st July 2015 at 6:56 pm #64087
Some things get confused. You should exit navigatorICS, power down the Malta, stop the HDI service start the HDI service, power cycle the probe, power up the Malta and try again.
Also is looks like your target setting is for a 34K and an interAptiv however I don’t think that would cause the problem you are seeing.
In the future you should use the Partner Portal for these types of questions.29th January 2015 at 11:16 am #64137
Should work! Why do you think it doesn’t?21st January 2015 at 7:20 pm #64124
There are several way to initialize the instruction and data caches. I use Index Store Tag which invalidates a cache line. See:
https://community.imgtec.com/developers/mips/resources/training-courses/mips-basic-training-course/ for caches video, slides and example code for more information.27th October 2014 at 5:10 pm #64139
This is a link to a sorting example. You could just use it and return the first and last elements of the array.22nd September 2014 at 9:47 pm #64150
Your target board should come with instructions on how to download software. Usually you would boot Linux/Android tftp (function of your boot rom/flash) and then use NFS to mount the file system. Or have everything on a hard drive or Flash and bot from there.22nd September 2014 at 9:43 pm #64147
Works for me. Try it again it could have been an outage.20th August 2014 at 3:46 am #64159
There are interAptiv boards but you can’t buy them. The P5600 Core is just being release so there are no boards yet.20th August 2014 at 3:32 am #64156
An EHB is just to make sure that a mtc0 doesn’t put the following instructions into a hazard case. It has no effect on the software interrupt. The sw interrupt needs three cycles for pipeline flush before it is raised and pending. EHB doesn’t change the pipeline flush logic. So this is normal behavior.
Usually the software interrupt is enabled, while in an interrupt routine, to preform task that don’t need as high an interrupt priority, By the time the interrupt routine does a eret the software interrupt will be raised and taken if its the highest priority interrupt pending.23rd July 2014 at 6:08 pm #64166
There’s more to an answer then I would like to cover in just a comment here. I will direct you to the training videos on the subject. These videos are on the imgtec.com web site undter community.>mips insider >Developer Resources. There you will find the training videos.
Code examples are provides with some of the videos.
The specific group of videos for multi-threading are here:
You will need a login but it is free and you can set one up automatically.14th May 2014 at 8:24 pm #64169
The clocks are independent so they would never be the same but I would think they would be close. How off are the clocks?9th May 2014 at 5:16 pm #64596
Assuming $re1 is just sudo code for an actual register then your code is correct. (I also assume you have a reason to store the frame pointer, for that you could have also used sw $sp, 0($fp).9th May 2014 at 5:03 pm #64174
Assuming you want to store to the address and the address in a virtual address and not a physical address:
This codes stores 42 to the virtual address 0x10008000
li t0, 42 # load the immediate value 42 to register t0
la, t1, 0x10008000 # load address to be stored to to t1
sw, t0, t1 # store word (32 bits) from register t0 to register t1