News Releases

Industry’s Highest Performance, Most Scalable RISC-V IP Core Already Adopted for Next-Generation Automotive Applications San Jose, Calif., Dec. 12, 2022 -- As the shift toward RISC-V accelerates ac...

Mobileye Adopts New MIPS eVocore RISC-V CPUs; RISC-V Architecture to Help Drive Future of Vehicle Safety San Jose, Calif., December 12, 2022- MIPS, a leading developer of highly scalable RISC proc...

Building on 35 years of innovation in RISC processor development, MIPS’ strategic move to RISC-V is supported by Imperas RISC-V Reference Models, Verification IP, and test suites Oxford, United K...

 RISC-V Summit has always been the ideal venue to unveil new innovations that drive higher performance and greater scalability for today’s complex applications. And this year will be no differen...

Architecture Will Accelerate Innovation in Open Computing SAN JOSE, Calif., Aug. 30, 2022 /PRNewswire/ -- MIPS, a leading developer of highly scalable RISC processor IP, announced it is working wi...

July 11th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest updates for RVVI (RISC-V Verification Interface) for RISC-V processor verification with...

Previews the first IP solutions in the eVocore™ product lineup: P8700 and I8500 multiprocessors SAN JOSE, Calif. – May 10, 2022 – MIPS, a leading developer of highly scalable RISC processor IP,...

SILICON VALLEY, CA, USA - March 28, 2022. Ashling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support MIPS RISC-V ISA based IP cores. RiscFree™ is Ashling�...

Oxford, United Kingdom – November 29th, 2021 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with MIPS, Inc., the processor technology company focused on the ...

SANTA CLARA, Calif., March 1, 2021 /PRNewswire/ — Wave Computing, Inc. (“Wave”) and its subsidiaries including MIPS Tech, the processor technology company focused on the commercialization of ...