MIPS Architectures

MIPS is a simple, streamlined, highly scalable RISC architecture that is available for licensing. Over time, the architecture has evolved, acquired new technologies and developed a robust ecosystem and comprehensive industry support. Its fundamental characteristics – such as the large number of registers, the number and the character of the instructions, and the visible pipeline delay slots – enable the MIPS architecture to deliver the highest performance per square millimeter for licensable IP cores, as well as high levels of power efficiency for today’s SoC designs.

The MIPS architecture is one of the most widely supported of all processor architectures, with a broad infrastructure of standard tools, software and services to help ensure rapid, reliable, cost effective development. Microprocessor developers who want maximum flexibility from processor IP have a solution in the MIPS architecture.

MIPS Architecture products include

The MIPS32® and MIPS64® instruction-set architectures, which are seamlessly compatible, allow customers to port from one generation to the next while preserving their investment in existing software.

microMIPS®, a code compression Instruction Set Architecture (ISA) comprised of 16- and 32- bit instructions, that provides similar performance to MIPS32 with a code size reduction of up to 25%.

Architecture modules that are encompassed as part of the base architecture include SIMD (Single Instruction Multiple Data operation), Virtualization, Multi-threading (MT) and DSP technologies.