MIPS offers a series of architecture modules that allow designers to extend their MIPS32, MIPS64 or microMIPS instruction sets for additional functionality.
Hardware multi-threading can make a single processor core appear and function like multiple separate cores for improved performance and efficiency. MIPS delivers this capability in several families of our licensable CPU IP products, providing a differentiated and highly efficient mechanism to achieve higher levels of performance and/or low latency context switching behavior. Find out more about MIPS Multi-threading.
The MIPS Virtualization (VZ) module provides the foundation for MIPS multi-domain security technology, and enables consolidation of multiple different embedded CPUs into a single core, resulting in lower silicon area and development effort, ultimately decreasing the overall cost and extending battery life.
The MIPS SIMD Architecture (MSA) incorporates a software-programmable solution into the CPU to handle emerging codecs or a small number of functions not covered by dedicated hardware. This programmable solution allows for increased system flexibility. In addition, the MSA is designed to accelerate many compute-intensive applications by enabling generic compiler support.
The MIPS DSP module offers licensees a programmable solution for DSP applications, allowing adaptation to changing market needs and extending the life of an SoC design. The DSP module comprises a set of instructions and state in the integer pipeline of MIPS cores and requires minimal additional logic to implement.
The MIPS MCU module provides key enhancements for microcontroller applications including enhanced handling of memory-mapped I/O registers and lower interrupt latencies.
The MIPS16e module is composed of 16-bit compressed code instructions, designed for the embedded processor market and situations with tight memory constraints. The core can execute both 16- and 32-bit instructions intermixed in the same program, and is compatible with both the MIPS32 and MIPS64 Architectures.