Current and next-generation consumer electronics such as mobile and home entertainment devices must deliver extremely high-quality audio, video, image, and graphics performance in order to be competitive. Enterprise applications benefit from technologies providing higher throughput data movement, especially important for scientific/high-performance computing and data mining. These advanced processing requirements are optimized and accelerated with SIMD (Single Instruction Multiple Data), important technology for modern CPU designs that improves performance by allowing efficient parallel processing of vector operations.
In consumer electronics, while dedicated, non-programmable hardware aids the CPU and GPU by handling heavy-duty multimedia codecs, the MIPS SIMD Architecture (MSA) technology incorporates a software-programmable solution into the CPU to handle emerging codecs or a small number of functions not covered by dedicated hardware. This programmable solution allows for increased system flexibility. In addition, the MSA is designed to accelerate many compute-intensive applications by enabling generic compiler support.
The MSA technology was implemented with strict adherence to RISC (Reduced Instruction Set Computer) design principles. MIPS architects designed the MSA with simple instructions that lead to less complex implementations. The carefully selected, simple SIMD instruction set is not only programmer- and compiler-friendly, but also hardware-efficient in terms of speed, area, and power consumption. The MSA technology specification is extensible and able to accommodate future requirements.
- 32 vector registers of 16 x 8-bit, 8 x 16-bit, 4 x 32-bit, and 2 x 64 bit vector elements
- Efficient vector parallel arithmetic operations on integer, fixed-point and floating-point data
- Operations on absolute value operands
- Rounding and saturation options available
- Full precision multiply and multiply-add
- Conversions between integer, floating-point, and fixed-point data
- Complete set of vector-level compare and branch instructions with no condition flag
- Vector (1D) and array (2D) shuffle operations
- Typed load and store instructions for endian-independent operation
- IEEE Standard for Floating-Point Arithmetic 754™-2008 compliant
- Element precise floating-point exception signaling
- Pre-defined scalable extensions for chips with more gates/transistors
- Accelerates compute-intensive applications in conjunction with leveraging generic compiler support
- Software-programmable solution for consumer electronics applications or functions not covered by dedicated hardware
- Emerging data mining, feature extraction, image and video processing, and human-computer interaction applications
- High-performance scientific computing