RISC-V ISA
eVocore IP: A New level of scalability for high-performance heterogeneous compute
eVocore CPUs are the first MIPS products based on the RISC-V open instruction set architecture (ISA) standard. These multiprocessors have unique features and a high level of scalability that make them ideal for compute-intensive tasks across a broad range of markets and applications such as automotive (ADAS, AV, IVI), on-device machine learning, 5G and wireless networking, data center and storage, and high-performance embedded applications.
With eVocore IP cores, you get the scalability and configurability you need to meet your specific application requirements. You can combine clusters of multi-threaded, multi-core CPUs – both eVocore processors as well as other accelerators – in unique configurations to achieve the right balance of performance and power consumption. A Coherence Manager maintains L2 cache and system-level coherency between all cores, main memory, and I/O devices.
With eVocore, you have a flexible foundation for heterogeneous compute.
eVocore P8700:
Superscalar Performance
This multiprocessing system combines a deep pipeline with multi-issue Out-of-Order (OoO) execution and multi-threading to deliver outstanding computational throughput. It has single-threaded performance greater than what is currently available in other RISC-V CPU IP offerings, and it can scale up to 64 clusters, 512 cores and 1,024 harts/threads.
P8700: Coherent Multi-core, Multi-cluster System
- Multi-issue superscalar Out of Order (OOO) with Multi-threading
- Enhanced Coherence Manager with L2$
- System interface:
eVocore I8500:
Best-in-Class Performance Efficiency
The I8500 is an in-order multiprocessing system with best-in-class power efficiency for use in SoC applications. Each I8500 core combines multi-threading and an efficient triple-issue pipeline to deliver outstanding computational throughput. The solution can scale up to 64 clusters, 512 cores and 2,048 harts/threads.
I8500: Coherent Multi-core, Multi-cluster System
- In-Order with Simultaneous Multi-threading (SMT)
- Enhanced Coherence Manager with L2$
- System interface:
Building on 35 Years of Innovation
The MIPS instruction set architecture (ISA) has powered billions of products for more than 35 years. Now, we’re building on the innovation of the MIPS ISA for RISC-V designs. Because of the many similarities between the RISC-V ISA and previous generations of the MIPS ISA, we can bring decades of development experience to the new eVocore products.
And because the RISC-V ISA lets you add custom features in the form of user defined instructions (UDIs), you can take advantage of the proven and powerful features of MIPS in RISC-V designs – all fully compatible with off-the-shelf RISC-V development tools and software libraries.
New eVocore IP cores provide support for privileged hardware virtualization, user defined custom extensions, multi-threading, SIMD, hybrid debug, functional safety, and much more.
Develop
Get started on your design with MIPS eVocore CPUs! Learn more about the growing ecosystem of tools and software supporting our family of RISC-V CPU cores.
LLVM compiler support
RiscFree™ for RISC-V IDE and Debugger
Ashling’s Integrated Development Environment (IDE) and Debugger for RISC-V based development
Opella-XD probe
With standard JTAG interface to debug hardware targets
Linux support
Intel Pathfinder for RISC-V
Platform designed to deliver new capabilities for pre-silicon development
FPGA platform for application development
Supports additional peripherals including DDR, Flash, Ethernet, SPI, UART, I2C. Includes Linux support. Available in Q1 2023.