I-Class I6500-F Processor Core

CPU IP Designed for Safety Critical Systems in an Autonomous Age

Artificial Intelligence (AI) techniques are increasingly used to give products greater awareness of their environment and, from this, a greater ability to control and automate functionality. We are seeing the emergence of artificial neural networks across a wide range of systems, from consumer products to ADAS and autonomous driving to industrial applications and beyond.

With the adoption of AI techniques, the required level of computing performance is much higher, and this is being addressed by a combination of dedicated accelerators and general purpose CPU-based compute capability. High-performance multiprocessor systems are a must.

In areas such as the automotive and industrial markets, Functional safety is also critical. These systems must be designed from the system level with a high degree of redundancy. The first step is to ensure that the product implements the correct behavior by design, which is managed by rigorous QMS processes. Safety-critical products must also detect and respond to errors that can occur during operation. Systems must be designed to adhere to industry standards for functional safety including ISO 26262 for automotive and IEC 61508 for industrial applications.

The MIPS I6500-F is the newest IP core in MIPS CPU product line, extending the variety and scalability of “off-the-shelf” licensable cores based on the proven and respected MIPS64 architecture to address the functional safety and performance requirements of emerging autonomous applications.

The MIPS I6500-F SEooC package is designed for systems requiring the highest level of functional safety: ASIL D. To achieve this level, not every IP core needs to reach the ASIL D. Instead the system is decomposed into IP that each reach a level similar to ASIL B but with enhanced fault detection time and fault coverage.

The additional functional redundancy built into the MIPS I6500-F includes:

Heterogeneous Inside and Out

In embedded applications the computational workload is naturally multi-threaded but each thread will require a specific performance level. With the emergence of AI, many of these computational threads are sufficiently specialized to benefit from dedicated computational elements or accelerators. The MIPS I6500-F is well positioned to enable these complex systems.

Multi-threading

The performance of a CPU depends on minimizing the latency to the system memory. Even with a cache hierarchy, the CPU still stalls while waiting for data and this is where multi-threading offers significant performance improvements by running additional threads during these times.

Multi-threading is a more area-efficient alternative to the use of additional cores and offers a typical 40% performance boost for the execution of two threads simultaneously instead of sequentially.

Heterogeneous Combinations of Cores

Threads with high performance requirements can be run as a single thread on a core and this core can be optimized to maximize this single-threaded performance with increased resources such as level 1 cache size and FPU/SIMD capabilities. Other threads can share other cores for greater efficiency while lower-performance threads can be run on cores that are optimized for low power consumption with independently controlled clock frequency and voltage.

The I6500-F allows any combination of core configurations within a single cluster to optimally align to the system needs.

Accelerator Integration

Specialist computational tasks such as artificial neural networks for AI achieve the highest performance with the greatest efficiency as dedicated accelerators. These accelerators need to work closely with the general purpose CPU cores to achieve the combination of flexibility from the CPU cores and efficient performance from the accelerators.

To enable this, the I6500-F provides very low communication latency through: