The MIPS P5600 delivers industry-leading 32-bit performance with class-leading low power characteristics in a silicon footprint significantly smaller than comparable alternatives in the industry.
The P5600 CPU core was designed for the performance and features required for mainstream consumer electronics including connected TVs and set-top boxes, and the rich, broad feature set extends its applicability into a variety of networking applications from residential gateways to network appliances, as well as high-performance compute in embedded applications.
The MIPS P5600 CPU is based on a wide issue, deeply out-of-order (OoO) implementation of the MIPS32 architecture, supporting up to six cores in a single cluster with high performance cache coherency. Complementing its raw horsepower, this core also includes 128-bit integer and floating point SIMD processing, hardware virtualization, and physical and virtual addressing capability enhancements.
Power Management
The MIPS P5600 processor IP core delivers top line performance while being the most efficient CPU core in its class, making it ideal for a wide range of applications in the rapidly growing connected consumer electronics market.
The P5600 builds upon the existing proAptiv family microarchitecture, adding 128-bit SIMD, hardware virtualization with hardware table walk, 40-bit eXtended Physical Addressing (XPA), and substantial gains in performance on system-oriented software workloads.
The P5600 CPU also achieves 5.4 CoreMark/MHz per core, and 3.5 DMIPS/MHz, matching or exceeding other high-end CPU IP cores.
The P5600 processor delivers this performance in a much smaller silicon footprint than leading IP core alternatives, achieving these results in up to 30% smaller silicon area, given a common process geometry, similar configurations and synthesis techniques used. SoC designers can use this efficiency advantage for significant cost and power savings, or to implement additional cores to deliver a performance advantage against competing silicon.
Documentation
P5600 Benefits
- 128-bit SIMD – accelerates execution of audio, video, graphics, imaging, speech and other DSP-oriented software algorithms, with instruction set designed for development in high level languages such as C, OpenCL
- MIPS multi-domain security technology based on hardware virtualization – ensuring that applications that need to be secure are effectively and reliably isolated from each other, as well as protected from non-secure applications
- Advanced addressing extensions for Enhanced Virtual Address (EVA) and eXtended Physical Address (XPA)
- Multiple context security platform for enterprise/consumer partitioning, secure content access, payments/transactions, and isolating secure schemes from numerous content sources
- Sophisticated branch prediction for maximizing utilization and performance on deeply pipelined CPU
- Load/Store bonding for optimum data movement performance
- Industry leading benchmark and real world performance at smaller area and power than competing solutions
- Broad software and ecosystem support and mature toolchain
- Available as synthesizable IP, for implementation in any process node, with standard cells and memories
Base Core Features
- 32-bit MIPS32® Release 5 Instruction Set Architecture
- High-performance, 16-stage, wide issue, out-of-order (OoO) pipeline
- L1 cache size for Instruction and Data of 32KB or 64KB each, 4-way set associative
- New high-performance dual-issue 128-bit SIMD Unit – optional
- Full hardware virtualization
- Programmable Memory Management Unit (MMU)
- Power Management Features
- EJTAG/PDtrace debug blocks and interface
Coherent Multi-Core Processor Features
- Superscalar, deeply OoO multi-core processor
- Advanced debug capabilities – PDtrace subsystem allows visibility to core- and cluster-level trace information
- Complete multi-core system designed for maximum cluster-level bandwidth
Specifications
| Target | TSMC 28HPM |
| Frequency | 1 GHz – 2+ GHz* |
| CoreMark/MHz (per core) | >5 |
| Total CoreMark @ 1.5GHz | >7500 per core |
| DMIPS/MHz (per core) | 3.5 |
| Total DMIPS @ 1.5GHz | >5250 per core |
Frequencies indicated are based on pre-production P5600 RTL and compared with results for fully floorplanned dual core proAptivimplementation, and range from 12T SVt area-optimized in worst case silicon corner, to 12T MVt speed-optimized typical corner silicon. Final production RTL results may vary.
Each base core configuration:
- 32KB Data/Inst L1 caches with parity, BIST
- New high-speed Integer + Floating Point (SP and DP) SIMD unit
- Fully-featured MMU, using multi-level TLB (I/D uTLBs + 128 entry VTLB + 1024 entry FTLB)
- PDtrace™ debug
Multi-core cluster configuration:
- Dual fully-configured P5600 cores per above
- Coherence Manager + integrated 1MB L2$ w/ECC
- One hardware IO Coherence Unit (IOCU) port
- Cluster level PDtrace
Implementation libraries/parameters – speed optimized, based on:
- TSMC 28HPM 12T standard cells + Synopsys memories
- Worst case, slow-slow corner silicon (zero temp, WCZ) with 10% OCV + 25ps clock jitter margins, except where noted at typical silicon