The MIPS P6600 is a 64-bit processor core that represents an evolution of the MIPS P-class family.
Building on the 32-bit P5600 CPU, and paving the way to future generations of high performance 64-bit MIPS processors, the P6600 is the most efficient mainstream high-performance CPU choice, enabling powerful multicore 64-bit SoCs with optimal area efficiency for applications in segments including home entertainment, networking, automotive, embedded high-performance compute and more.
The MIPS P6600 CPU is based on a wide issue, deeply out-of-order (OoO) implementation utilizing the latest release 6 of the MIPS64 architecture, supporting up to six cores in a single cluster with high performance cache coherency. Complementing this raw horsepower, the core includes 128-bit integer and floating point SIMD processing, hardware virtualization, and larger physical and virtual addressing space coming from the MIPS64 architecture.

The P6600 processor delivers performance in a smaller silicon footprint than leading IP core alternatives. SoC designers can use this efficiency advantage for cost savings, or to implement additional cores to deliver a performance advantage against competing silicon.
P6600 Benefits
- MIPS64 r6 architecture – provided larger virtual and physical addressing, plus higher performance on 64-bit operations and data movement. Leverages latest release 6 of MIPS64, with optimizations for running JITs, Javascript, Browsers, PIC, etc.
- MIPS multi-domain security technology based on hardware virtualization – ensuring that applications that need to be secure are effectively and reliably isolated from each other, as well as protected from non-secure applications
- Sophisticated branch prediction for maximizing utilization and performance on deeply pipelined CPU
- Broad software and ecosystem support and mature toolchain
- 128-bit SIMD – accelerates execution of audio, video, graphics, imaging, speech and other DSP-oriented software algorithms, with instruction set designed for development in high level languages such as C, OpenCL
- Multiple context security platform for enterprise/consumer partitioning, secure content access, payments/transactions, and isolating secure schemes from numerous content sources
- Load/Store bonding for optimum data movement performance
- Available as synthesizable IP for implementation in any process node, with standard cells and memories
Base Core Features
- 64-bit MIPS64® Release 6 Instruction Set Architecture
- High-performance, 16-stage, wide issue, out-of-order (OoO) pipeline
- L1 cache size for Instruction and Data of 32KB or 64KB each, 4-way set associative
- New high-performance dual-issue 128-bit SIMD Unit – optional
- Full hardware virtualization
- Programmable Memory Management Unit (MMU)
- Power Management Features
- EJTAG debug block and interface
Coherent Multi-Core Processor Features
- Superscalar, deeply OoO multi-core processor
- Advanced debug capabilities – PDtrace subsystem allows visibility to core- and cluster-level trace information
- Complete multi-core system designed for maximum cluster-level bandwidth

Specifications
Target | TSMC 28HPM |
Frequency | 1 GHz – 2+ GHz* |
CoreMark/MHz (per core) | >5 |
Total CoreMark @ 1.5GHz | >7500 per core |
DMIPS/MHz (per core) | 3.5 |
Total DMIPS @ 1.5GHz | >5250 per core |
Frequencies indicated range from 12T SVt area-optimized in worst case silicon corner, to 12T MVt speed-optimized typical corner silicon. Final production RTL results may vary.
Each base core configuration:
- 32KB Data/Inst L1 caches with parity, BIST
- High-speed Integer + Floating Point (SP and DP) SIMD unit
- Fully-featured MMU, using multi-level TLB
(I/D uTLBs + 128 entry VTLB + 1024 entry FTLB)
Multi-core cluster configuration:
- Dual fully-configured P6600 cores per above
- Coherence Manager + integrated 1MB L2$ w/ECC
- One hardware IO Coherence Unit (IOCU) port
Implementation libraries/parameters – speed optimized, based on:
- TSMC 28HPM 12T standard cells + Synopsys memories
- Worst case, slow-slow corner silicon (zero temp, WCZ)
with 8% OCV + 25ps clock jitter margins, except where noted at typical silicon